Hi Mark,
I'd like to send v4 of this series soon, hopefully for the last time. Would
you be able to reply to the two issues that are still left and discussed below
? That would be really appreciated.
On Wednesday 20 November 2013 22:54:58 Laurent Pinchart wrote:
> On Tuesday 19 November 2013 18
Hi Mark,
On Tuesday 19 November 2013 18:19:36 Mark Rutland wrote:
> On Tue, Nov 19, 2013 at 05:00:40PM +, Laurent Pinchart wrote:
> > On Tuesday 19 November 2013 16:28:21 Mark Rutland wrote:
> > > On Tue, Nov 19, 2013 at 02:45:42PM +, Laurent Pinchart wrote:
> > > > MSTP clocks are gate cl
On Tue, Nov 19, 2013 at 05:00:40PM +, Laurent Pinchart wrote:
> Hi Mark,
>
> Thank you for the quick review, much appreciated.
>
> On Tuesday 19 November 2013 16:28:21 Mark Rutland wrote:
> > On Tue, Nov 19, 2013 at 02:45:42PM +, Laurent Pinchart wrote:
> > > MSTP clocks are gate clocks c
Hi Mark,
Thank you for the quick review, much appreciated.
On Tuesday 19 November 2013 16:28:21 Mark Rutland wrote:
> On Tue, Nov 19, 2013 at 02:45:42PM +, Laurent Pinchart wrote:
> > MSTP clocks are gate clocks controlled through a register that handles
> > up to 32 clocks. The register is o
On Tue, Nov 19, 2013 at 02:45:42PM +, Laurent Pinchart wrote:
> MSTP clocks are gate clocks controlled through a register that handles
> up to 32 clocks. The register is often sparsely populated.
Does that mean some clocks aren't wired up, or that some clocks don't
exist at all?
What is the b
MSTP clocks are gate clocks controlled through a register that handles
up to 32 clocks. The register is often sparsely populated.
Those clocks are found on Renesas ARM SoCs.
Cc: devicetree@vger.kernel.org
Signed-off-by: Laurent Pinchart
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.../bindings/clock/renesas,cpg-mstp-clocks.txt |
