On Tue, Aug 25, 2015 at 12:16 PM, punnaiah choudary kalluri
punn...@xilinx.com wrote:
Hi Rob,
On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring robherri...@gmail.com wrote:
On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding
Hi Rob,
On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring robherri...@gmail.com wrote:
On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
On 08/06/2015 05:19 AM, Punnaiah Choudary Kalluri wrote:
[...]
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+gather dma mode
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+ source AXI
On Mon, Aug 24, 2015 at 7:17 PM, Lars-Peter Clausen l...@metafoo.de wrote:
On 08/06/2015 05:19 AM, Punnaiah Choudary Kalluri wrote:
[...]
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+gather dma mode
+- xlnx,ratectrl:
On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Hi Moritz,
Thanks. I will take care of these suggestions in next version
Regards,
Punnaiah
On Fri, Aug 21, 2015 at 10:12 PM, Moritz Fischer
moritz.fisc...@ettus.com wrote:
Hi all,
sorry for HTML mail spam last night ... couple of nits below
On Wed, Aug 5, 2015 at 8:19 PM, Punnaiah
Hi all,
sorry for HTML mail spam last night ... couple of nits below
On Wed, Aug 5, 2015 at 8:19 PM, Punnaiah Choudary Kalluri
punnaiah.choudary.kall...@xilinx.com wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah
On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote:
+- interrupts: Should contain DMA channel interrupt
channel interrupt or interrupts, former says it is plural
ZynqMP DMA has single interrupt for each channel So, that is the reason
i have explicitly mentioned it as
On 08/20/2015 08:18 AM, Vinod Koul wrote:
On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote:
+- interrupts: Should contain DMA channel interrupt
channel interrupt or interrupts, former says it is plural
ZynqMP DMA has single interrupt for each channel So, that is the
On Thu, Aug 20, 2015 at 11:22 AM, Vinod Koul vinod.k...@intel.com wrote:
On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri
On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
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