Re: [PATCHv1 0/2] Adding driver for Xilinx LogiCORE IP mailbox.

2015-05-27 Thread Michal Simek
On 05/26/2015 06:12 PM, Moritz Fischer wrote: On Mon, May 25, 2015 at 6:56 AM, Jingoo Han jingooh...@gmail.com wrote: On Monday, May 25, 2015 3:05 PM, Michal Simek wrote: On 05/22/2015 08:03 PM, Moritz Fischer wrote: This patchset adds mailbox framework integration for the Xilinx LogiCORE IP

Re: [PATCHv1 0/2] Adding driver for Xilinx LogiCORE IP mailbox.

2015-05-26 Thread Moritz Fischer
On Mon, May 25, 2015 at 6:56 AM, Jingoo Han jingooh...@gmail.com wrote: On Monday, May 25, 2015 3:05 PM, Michal Simek wrote: On 05/22/2015 08:03 PM, Moritz Fischer wrote: This patchset adds mailbox framework integration for the Xilinx LogiCORE IP mailbox. The Xilinx LogiCORE IP mailbox is a

Re: [PATCHv1 0/2] Adding driver for Xilinx LogiCORE IP mailbox.

2015-05-25 Thread Michal Simek
On 05/22/2015 08:03 PM, Moritz Fischer wrote: This patchset adds mailbox framework integration for the Xilinx LogiCORE IP mailbox. The Xilinx LogiCORE IP mailbox is a fpga softcore that allows interprocessor communication between AXI4 stream / memory mapped processors. Changes from v0:

Re: [PATCHv1 0/2] Adding driver for Xilinx LogiCORE IP mailbox.

2015-05-25 Thread Jingoo Han
On Monday, May 25, 2015 3:05 PM, Michal Simek wrote: On 05/22/2015 08:03 PM, Moritz Fischer wrote: This patchset adds mailbox framework integration for the Xilinx LogiCORE IP mailbox. The Xilinx LogiCORE IP mailbox is a fpga softcore that allows interprocessor communication between AXI4

[PATCHv1 0/2] Adding driver for Xilinx LogiCORE IP mailbox.

2015-05-22 Thread Moritz Fischer
This patchset adds mailbox framework integration for the Xilinx LogiCORE IP mailbox. The Xilinx LogiCORE IP mailbox is a fpga softcore that allows interprocessor communication between AXI4 stream / memory mapped processors. Changes from v0: - - Several stylistic issues -