On Thu, Jun 04, 2015 at 05:27:28PM -0500, Dinh Nguyen wrote:
This is my mistake. I applied Alan Tull's patch for suspend-to-ram which
also touches drivers/edac/altera_edac.c.
Hi Boris,
On 6/5/15 4:17 AM, Borislav Petkov wrote:
On Thu, Jun 04, 2015 at 05:27:28PM -0500, Dinh Nguyen wrote:
This is my mistake. I applied Alan Tull's patch for suspend-to-ram which
also touches drivers/edac/altera_edac.c.
On 06/04/2015 10:26 AM, Dinh Nguyen wrote:
On 06/04/2015 09:28 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
On Thu, Jun 04, 2015 at 04:34:49PM -0500, Thor Thayer wrote:
OK. I'll refactor and resend. I was using Altera's internal for-next branch.
Use this one:
git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git#for-next
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
On 06/04/2015 05:06 PM, Borislav Petkov wrote:
On Thu, Jun 04, 2015 at 04:34:49PM -0500, Thor Thayer wrote:
OK. I'll refactor and resend. I was using Altera's internal for-next branch.
Use this one:
git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git#for-next
This is my mistake. I
On 06/04/2015 09:28 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs in preparation
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs in preparation for the Arria10 support.
Signed-off-by: Thor Thayer
