On Thu, 2015-06-25 at 08:55 +0200, Michal Simek wrote:
On 06/24/2015 10:36 PM, Paul Bolle wrote:
On Tue, 2015-06-23 at 11:00 -0700, Moritz Fischer wrote:
+MODULE_ALIAS(platform:xilinx-mailbox);
So I think this MODULE_ALIAS() is only useful if, in short, there's
a corresponding
On 06/24/2015 10:36 PM, Paul Bolle wrote:
On Tue, 2015-06-23 at 11:00 -0700, Moritz Fischer wrote:
+MODULE_ALIAS(platform:xilinx-mailbox);
So I think this MODULE_ALIAS() is only useful if, in short, there's a
corresponding platform_device created. Ie, a platform_device with a
name
On 06/25/2015 09:31 AM, Paul Bolle wrote:
On Thu, 2015-06-25 at 08:55 +0200, Michal Simek wrote:
On 06/24/2015 10:36 PM, Paul Bolle wrote:
On Tue, 2015-06-23 at 11:00 -0700, Moritz Fischer wrote:
+MODULE_ALIAS(platform:xilinx-mailbox);
So I think this MODULE_ALIAS() is only useful if, in
On 06/25/2015 11:35 AM, Paul Bolle wrote:
On Thu, 2015-06-25 at 09:47 +0200, Michal Simek wrote:
It has to be platform_device somewhere for sure.
In past we had folder in arch/microblaze/platform folder.
Currently you can add this code to for example
arch/microblaze/kernel/platform.c
But as
On Thu, 2015-06-25 at 09:47 +0200, Michal Simek wrote:
It has to be platform_device somewhere for sure.
In past we had folder in arch/microblaze/platform folder.
Currently you can add this code to for example
arch/microblaze/kernel/platform.c
But as I said I don't think it is really
On Tue, 2015-06-23 at 11:00 -0700, Moritz Fischer wrote:
+MODULE_ALIAS(platform:xilinx-mailbox);
So I think this MODULE_ALIAS() is only useful if, in short, there's a
corresponding platform_device created. Ie, a platform_device with a
name xilinx-mailbox that will fire of a
The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
interprocessor communication via AXI4 memory mapped / AXI4 stream
interfaces.
It is single channel per core and allows for transmit and receive.
Changes from v4:
- Have separate mbox_ops structs for polling / irq mode
- Moved clk
Hey Moritz-
Just a couple more nits, nothing big. Looks pretty clean!
On Tue, Jun 23, 2015 at 11:00:02AM -0700, Moritz Fischer wrote:
The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
interprocessor communication via AXI4 memory mapped / AXI4 stream
interfaces.
It is single
On 06/23/2015 08:00 PM, Moritz Fischer wrote:
The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
interprocessor communication via AXI4 memory mapped / AXI4 stream
interfaces.
It is single channel per core and allows for transmit and receive.
Changes from v4:
- Have separate
