Quoting David Lanzendörfer (2013-12-16 13:54:21)
Hi
that takes the MMC clock (and only the MMC clock) and does the setup
(it's basically configuring two values, sample and output, into the
clock register). I really don't know what does this do/why is it
required/when is it used; I'm
Hi Mike et al,
El 15/12/13 01:51, Mike Turquette escribió:
clk_set_phase has been proposed before and now may be the time to add
it. There are two things that need to be addressed:
1) what are the values for the phase? This needs to work for others that
must set clk phase, so we need to
Hi,
On 12/16/2013 09:55 PM, Emilio López wrote:
Hi Mike et al,
El 15/12/13 01:51, Mike Turquette escribió:
clk_set_phase has been proposed before and now may be the time to add
it. There are two things that need to be addressed:
1) what are the values for the phase? This needs to work for
Hi
that takes the MMC clock (and only the MMC clock) and does the setup
(it's basically configuring two values, sample and output, into the
clock register). I really don't know what does this do/why is it
required/when is it used; I'm cc'ing Hans and David who can hopefully
explain that part.
Hi,
On Tue, Dec 17, 2013 at 4:55 AM, Emilio López emi...@elopez.com.ar wrote:
I also saw a similar requirement from the gmac people (on cc too), who
needed to set the phy type (or something like that) on one of the clock
The GMAC clock register controls the tx clock source (a mux) and the
On Thursday 12 December 2013, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Add a altr,socfpga-sdmmc-sdr-clk clock type in the SOCFPGA clock driver.
This
clock type is not really a clock for say, but a mechanism to set the phase
shift of the clock that is used to feed
Dear Arnd
On 12/15/2013 05:33 AM, Arnd Bergmann wrote:
On Thursday 12 December 2013, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Add a altr,socfpga-sdmmc-sdr-clk clock type in the SOCFPGA clock driver. This
clock type is not really a clock for say, but a mechanism to set
Quoting zhangfei (2013-12-14 18:18:45)
Dear Arnd
On 12/15/2013 05:33 AM, Arnd Bergmann wrote:
On Thursday 12 December 2013, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Add a altr,socfpga-sdmmc-sdr-clk clock type in the SOCFPGA clock driver.
This
clock type is
From: Dinh Nguyen dingu...@altera.com
Add a altr,socfpga-sdmmc-sdr-clk clock type in the SOCFPGA clock driver. This
clock type is not really a clock for say, but a mechanism to set the phase
shift of the clock that is used to feed the SD/MMC CIU's clock. This clock does
not have parent so it is
