Hi Andy,
On Fri, Sep 12, 2014 at 02:28:06PM -0500, Andy Gross wrote:
+Example device nodes:
+
+ hs_phy: phy@100f8800 {
+ compatible = qcom,dwc3-hs-usb-phy;
+ reg = 0x100f8800 0x30;
Just wanted to point out that in our downstream code, the
Hi,
On Tue, Sep 16, 2014 at 11:15:43AM -0700, Jack Pham wrote:
Hi Andy,
On Fri, Sep 12, 2014 at 02:28:06PM -0500, Andy Gross wrote:
+Example device nodes:
+
+ hs_phy: phy@100f8800 {
+ compatible = qcom,dwc3-hs-usb-phy;
+ reg = 0x100f8800
From: Ivan T. Ivanov iiva...@mm-sol.com
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
