On 10/26/2015 11:26 AM, Bharat Kumar Gogada wrote:
>>> + device_type = "pci";
>>> + interrupt-parent = <&gic>;
>>> + interrupts = < 0 118 4
>>> + 0 116 4
>>> + 0 115 4 // MSI_1 [63...32]
>>> + 0 114 4 >;
> > + device_type = "pci";
> > + interrupt-parent = <&gic>;
> > + interrupts = < 0 118 4
> > + 0 116 4
> > + 0 115 4 // MSI_1 [63...32]
> > + 0 114 4 >; // MSI_0 [31...0]
>
> Better write these as tuple
Hello,
I've got a few comments below.
On Sat, Oct 17, 2015 at 12:52:18PM +0530, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kiran Gummaluri
> ---
> Added MSI domain implementation for hand
On Saturday 17 October 2015 12:52:18 Bharat Kumar Gogada wrote:
> + "msi_1, msi_0": interrupt asserted when msi is recieved
Better avoid underscores in DT, use "msi0" instead of "msi_0".
> +- interrupt-map-mask and interrupt-map: standard PCI properties to define the
> + mapping of th
