Hi Karol,
Thank you for the patch.
On 04/12/2012 08:45 PM, Karol Lewandowski wrote:
Signed-off-by: Karol Lewandowski k.lewando...@samsung.com
Cc: Tomasz Stanislawski t.stanisl...@samsung.com
---
drivers/media/video/s5p-tv/hdmi_drv.c | 90
++---
1 files
Hi Karol,
Thanks for the patch.
Please refer to the comments below.
On 04/12/2012 08:45 PM, Karol Lewandowski wrote:
Includes v4l2/dt helper function (hdmi_of_get_i2c_subdev() that probably
should be implemented in v4l2 core itself.
Signed-off-by: Karol Lewandowski k.lewando...@samsung.com
* Stephen Warren wrote:
On 04/12/2012 11:44 AM, Thierry Reding wrote:
[...]
And given that, I don't think we should name the node after some
OS-specific software concept. Device tree is intended to model hardware.
[...]
Maybe one solution would be to have a top-level DRM device with a
On 21.03.2012 20:11, Karol Lewandowski wrote:
Changes since v2:
- Merge device type and flags into flat bitmask named quirks -
Consequently, treat s3c24xx as baseline hardware platform and
support all hw variations via quirks [Suggested by Mark Brown]
Changes since v1:
- Move
On Tue, Apr 10, 2012 at 05:06:27PM +0200, Thierry Reding wrote:
In order to get rid of the global namespace for PWM devices, this commit
provides an alternative method, similar to that of the regulator or
clock frameworks, for registering a static mapping for PWM devices. This
works by
On Tue, Apr 10, 2012 at 05:06:39PM +0200, Thierry Reding wrote:
This commit adds very basic support for device tree probing. Currently,
only a PWM and a list of distinct brightness levels can be specified.
Enabling or disabling backlight power via GPIOs is not yet supported.
Reviewed-by: Mark
* Hiroshi Doyu wrote:
From: Hiroshi DOYU hd...@nvidia.com
Add device tree support for Tegra30 IOMMU(SMMU).
Signed-off-by: Hiroshi DOYU hd...@nvidia.com
---
.../devicetree/bindings/arm/tegra/tegra30-smmu.txt | 19 +++
arch/arm/boot/dts/tegra30.dtsi |
* Hiroshi Doyu wrote:
From: Hiroshi DOYU hd...@nvidia.com
Add device tree support for Tegra30 IOMMU(SMMU).
Signed-off-by: Hiroshi DOYU hd...@nvidia.com
---
drivers/iommu/tegra-smmu.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
I would expect the binding
On 04/12/2012 11:14 PM, David Daney wrote:
From: David Daney david.da...@cavium.com
v3: Integrate changes from Lars-Peter Clausen to make better use of
the of_*() infrastructure. Get rid of ugly #ifdefs.
v2: Update bindings to use reg insutead of cell-index
v1: Unchanged from the
* Hiroshi Doyu wrote:
Thierry Reding wrote:
* Hiroshi Doyu wrote:
+ smmu: smmu@7000f000 {
+ compatible = nvidia,tegra30-smmu;
+ reg = 0x7000f000 0x400/* controller registers */
+ 0x6000c000 0x150/* AHB Arbitration registers */
+
On Thu, Apr 12, 2012 at 7:24 AM, Viresh Kumar viresh.ku...@st.com wrote:
We must use pinctrl framework instead of defining per SoC pinmux drivers. This
patch removes existing padmux support present for SPEAr platform.
Signed-off-by: Viresh Kumar viresh.ku...@st.com
FWIW: Acked-by: Linus
On Thu, Apr 12, 2012 at 7:24 AM, Viresh Kumar viresh.ku...@st.com wrote:
This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file
for SPEAr pinctrl drivers.
Signed-off-by: Viresh Kumar viresh.ku...@st.com
Looks good to me.
Acked-by: Linus Walleij linus.wall...@linaro.org
On Thu, Apr 12, 2012 at 7:24 AM, Viresh Kumar viresh.ku...@st.com wrote:
This adds pinctrl driver for SPEAr3xx family. SPEAr3xx family supports three
families: SPEAr300, SPEAr310 and SPEAr320.
Signed-off-by: Viresh Kumar viresh.ku...@st.com
Big but easy to read and looks correct, so:
On Thu, Apr 12, 2012 at 7:24 AM, Viresh Kumar viresh.ku...@st.com wrote:
Signed-off-by: Viresh Kumar viresh.ku...@st.com
Some blurb message maybe? Anyway:
Acked-by: Linus Walleij linus.wall...@linaro.org
Yours,
Linus Walleij
___
devicetree-discuss
This commit adds the device node required to probe NVIDIA Tegra 20 GART
hardware from the device tree.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
---
arch/arm/boot/dts/tegra20.dtsi |6 ++
arch/arm/mach-tegra/board-dt-tegra20.c |1 +
2 files changed, 7
This commit adds device tree support for the GART hardware available on
NVIDIA Tegra 20 SoCs.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
---
.../devicetree/bindings/iommu/nvidia,tegra20-gart.txt| 14 ++
drivers/iommu/tegra-gart.c
From: Vandana Salve vsa...@nvidia.com
Pass the correct gart device pointer.
Reviewed-by: Vandana Salve vsa...@nvidia.com
Tested-by: Vandana Salve vsa...@nvidia.com
Reviewed-by: Hiroshi Doyu hd...@nvidia.com
Reviewed-by: Bharat Nihalani bnihal...@nvidia.com
Signed-off-by: Hiroshi DOYU
On 04/13/2012 03:18 AM, Thang Nguyen wrote:
Thanks Jeff and Sergei,
As your suggestion, I will separate the patch into smaller patches and
support more features on the SATA DWC driver. The patches I intend to do
on the SATA DWC are as below:
- Support hardreset: currently the hardreset is not
This commit adds an empty of_property_match_string() function for
!CONFIG_OF builds.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
---
include/linux/of.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/include/linux/of.h b/include/linux/of.h
index e3f942d..937ca14
This commit adds an empty of_parse_phandle_with_args() function for
!CONFIG_OF builds.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
---
include/linux/of.h |9 +
1 file changed, 9 insertions(+)
diff --git a/include/linux/of.h b/include/linux/of.h
index
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, April 11, 2012 7:14 PM
To: Karicheri, Muralidharan
Cc: devicetree-discuss@lists.ozlabs.org
Subject: Re: standalone dtc compiler build from
git://git.jdl.com/software/dtc.git gives
-Original Message-
From: devicetree-discuss-bounces+m-karicheri2=ti@lists.ozlabs.org
[mailto:devicetree-discuss-bounces+m-karicheri2=ti@lists.ozlabs.org] On
Behalf Of
Karicheri, Muralidharan
Sent: Friday, April 13, 2012 11:26 AM
To: Stephen Warren
Cc:
From: Dong Aisheng dong.aish...@linaro.org
The driver has mux and config support while the gpio is still
not supported.
For select input setting, the driver will handle it internally
and do not need user to take care of it.
The pinctrl-imx core driver will parse the dts file and dynamically
From: Dong Aisheng dong.aish...@linaro.org
---
This patch is used for test the new pinctrl driver.
Signed-off-by: Dong Aisheng dong.aish...@linaro.org
---
arch/arm/boot/dts/imx6q-arm2.dts |4 +++
arch/arm/boot/dts/imx6q.dtsi | 40
On 04/11/2012 11:24 PM, Viresh Kumar wrote:
This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file
for SPEAr pinctrl drivers.
+int __devinit spear_pinctrl_probe(struct platform_device *pdev,
+ struct spear_pinctrl_machdata *machdata)
...
+ pmx-vbase =
On 04/11/2012 11:24 PM, Viresh Kumar wrote:
This adds pinctrl driver for SPEAr3xx family. SPEAr3xx family supports three
families: SPEAr300, SPEAr310 and SPEAr320.
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
+Required subnode-properties:
+- st,pins : An array of
On 04/13/2012 02:56 AM, Florian Fainelli wrote:
Hi David,
[...]
+/*
+ * The address offset of the GPIO configuration register for a given
+ * line.
+ */
+static unsigned int bit_cfg_reg(unsigned int gpio)
+{
+ if (gpio 16)
+ return 8 * gpio;
+ else
+ return 8 * (gpio - 16) + 0x100;
+}
You
On 04/11/2012 11:24 PM, Viresh Kumar wrote:
Signed-off-by: Viresh Kumar viresh.ku...@st.com
Just a couple of minor comments below.
diff --git a/arch/arm/boot/dts/spear300-evb.dts
b/arch/arm/boot/dts/spear300-evb.dts
+ pinmux@9900 {
+ st,pinmux-mode=2;
Hi Rob,
On Mon, Feb 13, 2012 at 4:22 AM, Rob Herring robherri...@gmail.com wrote:
On 02/11/2012 11:22 AM, Dong Aisheng wrote:
Currently most code to get child count in kernel are almost same,
add a helper to implement this function for dt to use.
Signed-off-by: Dong Aisheng
On Sat, Apr 14, 2012 at 12:18 AM, Dong Aisheng b29...@freescale.com wrote:
From: Dong Aisheng dong.aish...@linaro.org
The driver has mux and config support while the gpio is still
not supported.
For select input setting, the driver will handle it internally
and do not need user to take care
On Fri, Apr 13, 2012 at 09:29:10AM +0530, Viresh Kumar wrote:
On 3/22/2012 9:20 PM, Stefan Roese wrote:
This patch adds support to configure the SPEAr EHCI OHCI driver via
device-tree instead of platform_data.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Viresh Kumar
The new debugging shows the value of integers and addresses read
from the device tree.
Signed-off-by: Simon Glass s...@chromium.org
---
lib/fdtdec.c | 22 --
1 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 42c3e89..3885634
Add a flash node to handle the NAND, including memory timings and
page / block size information.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
board/nvidia/dts/tegra2-seaboard.dts | 15 +++
1 files changed, 15
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
arch/arm/dts/tegra20.dtsi |6 ++
doc/device-tree-bindings/nand/nvidia-nand.txt | 68
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
arch/arm/dts/tegra20.dtsi |6 ++
Hi Scott,
On Fri, Apr 13, 2012 at 11:43 AM, Scott Wood scottw...@freescale.com wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia,
On 04/13/2012 02:01 PM, Simon Glass wrote:
Hi Scott,
On Fri, Apr 13, 2012 at 11:43 AM, Scott Wood scottw...@freescale.com wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
---
On Mon, Oct 17, 2011 at 10:41 AM, David Daney david.da...@cavium.com wrote:
On 10/17/2011 07:48 AM, Kumar Gala wrote:
On Sep 29, 2011, at 7:32 PM, Grant Likely wrote:
On Thu, Sep 29, 2011 at 04:31:12PM -0400, David Miller wrote:
From: David Daneydavid.da...@cavium.com
Your tree or mine,
Hi Scott,
On Fri, Apr 13, 2012 at 12:07 PM, Scott Wood scottw...@freescale.com wrote:
On 04/13/2012 02:01 PM, Simon Glass wrote:
Hi Scott,
On Fri, Apr 13, 2012 at 11:43 AM, Scott Wood scottw...@freescale.com wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with
On 04/13/2012 06:15 AM, Thierry Reding wrote:
* Hiroshi Doyu wrote:
Thierry Reding wrote:
* Hiroshi Doyu wrote:
+ smmu: smmu@7000f000 {
+ compatible = nvidia,tegra30-smmu;
+ reg = 0x7000f000 0x400/* controller registers */
+ 0x6000c000 0x150
On 04/13/2012 05:07 AM, Thierry Reding wrote:
* Hiroshi Doyu wrote:
From: Hiroshi DOYU hd...@nvidia.com
Add device tree support for Tegra30 IOMMU(SMMU).
Signed-off-by: Hiroshi DOYU hd...@nvidia.com
---
drivers/iommu/tegra-smmu.c | 10 ++
1 files changed, 10 insertions(+), 0
On 04/13/2012 04:22 AM, Hiroshi Doyu wrote:
From: Hiroshi DOYU hd...@nvidia.com
Add device tree support for Tegra30 IOMMU(SMMU).
+++ b/Documentation/devicetree/bindings/arm/tegra/tegra30-smmu.txt
I personally like the documentation to be named after the full
compatible value, so
On 04/13/2012 04:23 AM, Hiroshi Doyu wrote:
From: Hiroshi DOYU hd...@nvidia.com
Add device tree support for Tegra30 IOMMU(SMMU).
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
+#ifdef CONFIG_OF
+static struct of_device_id tegra_smmu_of_match[] __devinitdata = {
+
On 04/13/2012 07:08 AM, Thierry Reding wrote:
This commit adds device tree support for the GART hardware available on
NVIDIA Tegra 20 SoCs.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
Acked-by: Stephen Warren swar...@wwwdotorg.org
Here, I note that the GART aperture is
On 04/13/2012 07:08 AM, Thierry Reding wrote:
This commit adds the device node required to probe NVIDIA Tegra 20 GART
hardware from the device tree.
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c
b/arch/arm/mach-tegra/board-dt-tegra20.c
+ OF_DEV_AUXDATA(nvidia,tegra20-gart,
On 04/13/2012 12:08 PM, Andy Fleming wrote:
On Mon, Oct 17, 2011 at 10:41 AM, David Daneydavid.da...@cavium.com wrote:
On 10/17/2011 07:48 AM, Kumar Gala wrote:
On Sep 29, 2011, at 7:32 PM, Grant Likely wrote:
On Thu, Sep 29, 2011 at 04:31:12PM -0400, David Miller wrote:
From: David
On 04/13/2012 12:43 PM, Scott Wood wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
+++ b/doc/device-tree-bindings/nand/nvidia-nand.txt
+wp-gpio : GPIO of write-protect line, three
On 04/13/2012 12:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
+++ b/doc/device-tree-bindings/nand/nvidia-nand.txt
I'd prefer this be called nvidia,tegra20-nand.txt so filenames are named
according to
On 04/13/2012 04:05 PM, Stephen Warren wrote:
On 04/13/2012 12:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glasss...@chromium.org
+++ b/doc/device-tree-bindings/nand/nvidia-nand.txt
I'd prefer this be called
On 04/13/2012 03:58 PM, Stephen Warren wrote:
On 04/13/2012 12:43 PM, Scott Wood wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glasss...@chromium.org
+++ b/doc/device-tree-bindings/nand/nvidia-nand.txt
On 04/13/2012 03:21 PM, Scott Wood wrote:
On 04/13/2012 03:58 PM, Stephen Warren wrote:
On 04/13/2012 12:43 PM, Scott Wood wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glasss...@chromium.org
+++
On 04/13/2012 04:22 PM, Stephen Warren wrote:
On 04/13/2012 03:21 PM, Scott Wood wrote:
On 04/13/2012 03:58 PM, Stephen Warren wrote:
On 04/13/2012 12:43 PM, Scott Wood wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
From: Stephen Warren swar...@nvidia.com
ULPI PHYs have a reset signal, and different boards use a different GPIO
for this task. Add a property to device tree to represent this.
I'm not sure if adding this property to the EHCI controller node is
entirely correct; perhaps eventually we should have
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