On 7/8/2012 6:30 PM, Nicolas Pitre wrote:
On Fri, 6 Jul 2012, Mitch Bradley wrote:
On 7/6/2012 3:23 PM, David VomLehn (dvomlehn) wrote:
The kernel *must* go where it is linked, but the FDT contains only relative
references and is thus free to go anywhere. The same is true of ramdisks,
which
As Rob's clock binding support patch is now up on clk-next, I'd like to
draw attention on this patch again.
--
This patch adds support for using clock gates (clk-gate) from DT based
on Rob Herrings DT clk binding support for 3.6.
It adds a helper function to clk-gate to allocate all resources
Hi Thierry,
On Wed, Jul 11, 2012 at 7:48 AM, Thierry Reding
thierry.red...@avionic-design.de wrote:
On Wed, Jul 11, 2012 at 06:44:10AM +0200, Simon Glass wrote:
Hi Stephen,
On Fri, Jun 15, 2012 at 1:32 AM, Stephen Warren swar...@wwwdotorg.orgwrote:
On 06/13/2012 10:19 AM, Simon Glass
On Thu, Jul 12, 2012 at 10:21:01AM +0200, Simon Glass wrote:
Hi Thierry,
On Wed, Jul 11, 2012 at 7:48 AM, Thierry Reding
thierry.red...@avionic-design.de wrote:
On Wed, Jul 11, 2012 at 06:44:10AM +0200, Simon Glass wrote:
Hi Stephen,
On Fri, Jun 15, 2012 at 1:32 AM, Stephen Warren
On 11 July 2012 23:30, Thomas Abraham thomas.abra...@linaro.org wrote:
On 11 July 2012 23:19, Mark Brown broo...@opensource.wolfsonmicro.com wrote:
On Wed, Jul 11, 2012 at 09:10:59PM +0530, Thomas Abraham wrote:
Changes since v4:
- Includes the missing gpio request for slave select line gpio
From: Dong Aisheng dong.aish...@linaro.org
The General Purpose Registers (GPR) is used to select operating modes for
general features in the SoC, usually not related to the IOMUX itself,
but it does belong to IOMUX controller.
We simply provide an convient API for driver to call to write/read the
From: Dong Aisheng dong.aish...@linaro.org
The original pin registers table is derived from u-boot mainline,
but somehow it was found missing some mux functions for USBOTG_ID.
We added it at the bottom by following the exist pin function ids,
then it will not break the exist using of pin function
On Thu, Jul 12, 2012 at 05:07:59PM +0800, Dong Aisheng wrote:
From: Dong Aisheng dong.aish...@linaro.org
The General Purpose Registers (GPR) is used to select operating modes for
general features in the SoC, usually not related to the IOMUX itself,
but it does belong to IOMUX controller.
We
Hi Alex,
On Mon, Jul 9, 2012 at 8:08 AM, Alexandre Courbot acour...@nvidia.com wrote:
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
arch/arm/boot/dts/tegra20-ventana.dts | 31 +++
arch/arm/boot/dts/tegra20.dtsi| 2 +-
2 files changed, 32
On Thu, Jul 12, 2012 at 11:37:33AM +0200, Simon Glass wrote:
Hi Alex,
On Mon, Jul 9, 2012 at 8:08 AM, Alexandre Courbot acour...@nvidia.com wrote:
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
arch/arm/boot/dts/tegra20-ventana.dts | 31 +++
On Thu, Jul 12, 2012 at 05:48:46PM +0800, Hui Wang wrote:
Dong Aisheng wrote:
From: Dong Aisheng dong.aish...@linaro.org
The General Purpose Registers (GPR) is used to select operating modes for
general features in the SoC, usually not related to the IOMUX itself,
but it does belong to
On Thu, Jul 12, 2012 at 05:48:46PM +0800, Hui Wang wrote:
...
+
+int imx_pinctrl_gpr_read(u8 gpr)
+{
+ if (!imx_pinctrl)
+ return -EPROBE_DEFER;
+
+ return readl(imx_pinctrl-base + gpr);
Suppose the MSB of the register content is 1, how does the caller
From: Dong Aisheng dong.aish...@linaro.org
The General Purpose Registers (GPR) is used to select operating modes for
general features in the SoC, usually not related to the IOMUX itself,
but it does belong to IOMUX controller.
We simply provide an convient API for driver to call to write/read the
From: Dong Aisheng dong.aish...@linaro.org
The original pin registers table is derived from u-boot mainline,
but somehow it was found missing some mux functions for USBOTG_ID.
We added it at the bottom by following the exist pin function ids,
then it will not break the exist using of pin function
On 07/12/2012 02:15 AM, Sebastian Hesselbarth wrote:
As Rob's clock binding support patch is now up on clk-next, I'd like to
draw attention on this patch again.
--
This patch adds support for using clock gates (clk-gate) from DT based
on Rob Herrings DT clk binding support for 3.6.
It
This patch series adds device tree support for Synopsis Designware Mobile
Storage Host Controller.
The first patch converts the copy of controller device instance into a
reference. This is need to allow device resource management api to correctly
manage the resources allocated by the driver. The
The 'struct dw_mci' maintains a copy of the pdev-dev instance instead of
maintaining a reference to that 'struct device' instance. Any resource
allocated using the device resource management kernel API with the instance
of 'struct device' in 'struct dw_mci' is then incorrect. Fix this by
Instead of aborting the probe in case a slot initialization fails, allow
initialization of as many slots as possible. If there are atleast one
instance of slot that is successfully initialized, allow the driver probe
to succeed.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas
If the write protect pad of the controller is not connected to the write
protect pin of the slot, the driver should be notified of this condition
so that incorrect check for write protection by reading the WRTORT
register can avoided. The get_ro platform callback can be used for in
such cases, but
Add device tree based discovery support.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 108 +++
drivers/mmc/host/dw_mmc-pltfm.c| 24 +++
drivers/mmc/host/dw_mmc.c | 201
The instantiation of the Synopsis Designware controller on Exynos5250
include extension for SDR and DDR specific tx/rx phase shift timing
and CIU internal divider. In addition to that, the option to skip the
command hold stage is also introduced. Add support for these Exynos5250
specfic
On Tue, Jul 10, 2012 at 05:56:45AM -0700, Simon Glass wrote:
We want to add new options to this tool. In preparation for this, add
the concept of a current operation.
Signed-off-by: Simon Glass s...@chromium.org
---
fdtput.c | 37 ++---
1 files changed,
On Tue, Jul 10, 2012 at 05:56:46AM -0700, Simon Glass wrote:
This option allows the creation of new nodes in a dtb file. The syntax
is:
fdtput -c dtb_file node_path
The node_path contains the path of the node to be created. All path
components up to the final one must exist already.
On Tue, Jul 10, 2012 at 05:56:47AM -0700, Simon Glass wrote:
As with many fdt functions, report_error() should permit a namelen to
be specified, thus obviating the need for nul termination in strings
passed to it.
Signed-off-by: Simon Glass s...@chromium.org
Fair enough.
Acked-by: David
On Thu, Jul 12, 2012 at 06:11:05PM +0900, Kukjin Kim wrote:
And Mark, this touches various samsung stuff in arch/arm/ so if you're ok,
I'd like to pick this up in samsung tree. We don't want to see conflicts...
Well, simple conflicts aren't that big a deal... However, Thomas
mentioned that in
On 07/12/2012 02:14 PM, Rob Herring wrote:
+Required child properties:
+- reg : should contain the individual bit and polarity to control
+the clock gate. A polarity of 0 means that by setting the
+bit to 1 the clock passes through the clock gate while
+setting the bit to 0
Hello all!
We're building a new machine derived from MACH_AT91SAM9M10G45EK. As it is
very similar, we'd prefer to use DeviceTree, especially as we have slightly
different revisions already.
What we are planning to do:
- generate the machine dtb from dts and stored on the machine persistent
On 12 July 2012 18:32, Mark Brown broo...@opensource.wolfsonmicro.com wrote:
On Thu, Jul 12, 2012 at 06:11:05PM +0900, Kukjin Kim wrote:
And Mark, this touches various samsung stuff in arch/arm/ so if you're ok,
I'd like to pick this up in samsung tree. We don't want to see conflicts...
Hi Alex,
On Thu, Jul 12, 2012 at 12:11 PM, Alex Courbot acour...@nvidia.com wrote:
Hi Simon,
On Thu 12 Jul 2012 06:37:33 PM JST, Simon Glass wrote:
I would like to do something similar in U-Boot for Tegra, although
perhaps not right away. For now I will go with something considerably
This binding will apparently soon be in linux-next. Bring it in now
since we need to do something, and may as well try to target what
Linux will have.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Add new commit for pwm binding and node
arch/arm/dts/tegra20.dtsi
The new debugging shows the value of integers and addresses read
from the device tree and tidy up GPIO output.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Remove spurious newline from fdtdec_get_addr() debug output
- Tidy up fdtdec_decode_gpios() debug output
lib/fdtdec.c
Add LCD definitions and also a proposed binding for LCD displays.
The PWM is as per what will likely be committed to linux-next soon.
The displaymode binding comes from a proposal here:
http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html
The panel binding is new, and fills a
The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled
by one of the PWMs.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update seaboard LCD definitions for new fdt binding
Changes in v3:
- Use new upstream proposed LCD definitions
Hi David,
On Thu, Jul 12, 2012 at 2:37 PM, David Gibson
da...@gibson.dropbear.id.au wrote:
On Tue, Jul 10, 2012 at 05:56:45AM -0700, Simon Glass wrote:
We want to add new options to this tool. In preparation for this, add
the concept of a current operation.
Signed-off-by: Simon Glass
We want to add new options to this tool. In preparation for this, add
the concept of a current operation.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Change enum operation_t to oper_type
fdtput.c | 37 ++---
1 files changed, 26
This option allows the creation of new nodes in a dtb file. The syntax
is:
fdtput -c dtb_file node_path
The node_path contains the path of the node to be created. All path
components up to the final one must exist already. The final one must
not exist already.
Signed-off-by: Simon Glass
This option mimics mkdir's -p option. It automatically creates nodes
as needed along the path provided. If the node already exists, no
error is given.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update -p help message slightly
fdtput.c | 59
On Thu, Jul 12, 2012 at 8:16 PM, Richard Zhao linux...@gmail.com wrote:
[...]
+int imx_pinctrl_gpr_write(u8 gpr, u32 mask, u32 val)
+{
+ u32 reg;
+
+ if (!imx_pinctrl)
+ return -EPROBE_DEFER;
+
+ spin_lock(imx_pinctrl-gprlock);
spin_lock_irqsave? We don't know
On Thu, Jul 12, 2012 at 07:13:37PM +0530, Thomas Abraham wrote:
On 12 July 2012 18:32, Mark Brown broo...@opensource.wolfsonmicro.com wrote:
Well, simple conflicts aren't that big a deal... However, Thomas
mentioned that in order to test this he merged the SPI tree into your
tree so
This option mimics mkdir's -p option. It automatically creates nodes
as needed along the path provided. If the node already exists, no
error is given.
Signed-off-by: Simon Glass s...@chromium.org
Whole 5-part patchset applied.
Thanks,
jdl
___
On Tue, Jul 10, 2012 at 04:39:42PM +0530, AnilKumar Ch wrote:
This commit adds device tree support for tps65217 pmic. And usage
details are added to device tree documentation. Driver is tested
by using kernel module with regulator set and get APIs.
Applied, thanks.
signature.asc
Description:
On Wed, 11 Jul 2012, Mitch Bradley wrote:
On 7/8/2012 6:30 PM, Nicolas Pitre wrote:
On Fri, 6 Jul 2012, Mitch Bradley wrote:
For now, I'm putting the initrd at the end of memory and the dtb
below that. That seems to work, but I'm unsure whether or not
I'm just getting lucky.
[adding u-boot list]
On 07/12/2012 01:52 AM, Mitch Bradley wrote:
On 7/8/2012 6:30 PM, Nicolas Pitre wrote:
On Fri, 6 Jul 2012, Mitch Bradley wrote:
On 7/6/2012 3:23 PM, David VomLehn (dvomlehn) wrote:
The kernel *must* go where it is linked, but the FDT contains only relative
references
Dear Albert ARIBAUD,
In message 20120712233801.0411daa7@lilith you wrote:
If I'm not mistaken, yes U-Boot loads itself as high as it can, and I don't
know about the FDT, but no, U-Boot does not like to load initrd just
below that: it loads initrd where the boot commands tell it to, and the
Hi Rob,
On Thu, 12 Jul 2012 15:34:17 -0500, Rob Herring robherri...@gmail.com wrote:
[adding u-boot list]
On 07/12/2012 01:52 AM, Mitch Bradley wrote:
On 7/8/2012 6:30 PM, Nicolas Pitre wrote:
On Fri, 6 Jul 2012, Mitch Bradley wrote:
On 7/6/2012 3:23 PM, David VomLehn (dvomlehn)
On 07/13/12 01:16, Mark Brown wrote:
On Thu, Jul 12, 2012 at 07:13:37PM +0530, Thomas Abraham wrote:
On 12 July 2012 18:32, Mark Brownbroo...@opensource.wolfsonmicro.com wrote:
Well, simple conflicts aren't that big a deal... However, Thomas
mentioned that in order to test this he merged
On 07/12/12 00:41, Thomas Abraham wrote:
Add support for device based discovery.
Signed-off-by: Thomas Abrahamthomas.abra...@linaro.org
Acked-by: Jaswinder Singhjaswinder.si...@linaro.org
Acked-by: Grant Likelygrant.lik...@secretlab.ca
---
.../devicetree/bindings/spi/spi-samsung.txt|
On 07/12/2012 04:47 PM, Wolfgang Denk wrote:
Dear Albert ARIBAUD,
In message 20120712233801.0411daa7@lilith you wrote:
If I'm not mistaken, yes U-Boot loads itself as high as it can, and I don't
know about the FDT, but no, U-Boot does not like to load initrd just
below that: it loads
From: Dong Aisheng dong.aish...@linaro.org
The original pin registers table is derived from u-boot mainline,
but somehow it was found missing some mux functions for USBOTG_ID.
We added it at the bottom by following the exist pin function ids,
then it will not break the exist using of pin function
From: Dong Aisheng dong.aish...@linaro.org
The General Purpose Registers (GPR) is used to select operating modes for
general features in the SoC, usually not related to the IOMUX itself,
but it does belong to IOMUX controller.
We simply provide an convient API for driver to call to write/read the
On 07/12/2012 08:08 AM, Sebastian Hesselbarh wrote:
On 07/12/2012 02:14 PM, Rob Herring wrote:
+Required child properties:
+- reg : should contain the individual bit and polarity to control
+the clock gate. A polarity of 0 means that by setting the
+bit to 1 the clock passes
On 13 July 2012 04:08, Kukjin Kim kgene@samsung.com wrote:
Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems occur
following build error with s3c6400_defconfig.
drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
drivers/spi/spi-s3c64xx.c:1098: error:
Hi Mark,
On Thu, Jul 12, 2012 at 22:58:37, Mark Brown wrote:
On Tue, Jul 10, 2012 at 04:39:42PM +0530, AnilKumar Ch wrote:
This commit adds device tree support for tps65217 pmic. And usage
details are added to device tree documentation. Driver is tested
by using kernel module with
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