Hi,
On Wed, Dec 19, 2012 at 11:52:01AM +0530, Vivek Gautam wrote:
@@ -736,7 +1035,41 @@ static int __devinit samsung_usbphy_probe(struct
platform_device *pdev)
sphy-clk = clk;
- return usb_add_phy(sphy-phy, USB_PHY_TYPE_USB2);
+ sphy-has_usb3 = (sphy-cpu_type ==
Commit 50c8af4cf9, of: introduce for_each_matching_node_and_match()
renamed of_find_matching_node() to of_find_matching_node_and_match() and
created a new static inline of_find_matching_node() wrapper around the
new name. However, the change neglected to change the EXPORT_SYMBOL()
reference
On Wed, Dec 19, 2012 at 10:58 AM, Grant Likely
grant.lik...@secretlab.ca wrote:
Commit 50c8af4cf9, of: introduce for_each_matching_node_and_match()
renamed of_find_matching_node() to of_find_matching_node_and_match() and
created a new static inline of_find_matching_node() wrapper around the
2012/12/10 Stéphane Marchesin stephane.marche...@gmail.com
On Sun, Dec 9, 2012 at 10:26 PM, Inki Dae inki@samsung.com wrote:
2012/12/6 R. Chandrasekar rcse...@samsung.com
From: R. Chandrasekar rcse...@samsung.com
this patch set adds the driver support for the dithering
2012/12/12 Stéphane Marchesin stephane.marche...@gmail.com
On Mon, Dec 10, 2012 at 1:27 AM, Inki Dae inki@samsung.com wrote:
2012/12/10 Stéphane Marchesin stephane.marche...@gmail.com
On Sun, Dec 9, 2012 at 10:26 PM, Inki Dae inki@samsung.com wrote:
2012/12/6 R.
Well, the built-in driver works on systems that have more than one interface
and more than one BMC, and multiple IPMBs (and all of the other channel
types for that matter, and the driver handles all the multiplexing and nasty
addressing). There is, in fact, no arbitrary limit, and IBM tested
Tegra USB host driver is using port instance number,
to handle some of the hardware issues on SOC e.g. reset PORT0
twice etc. As instance number based handling looks ugly,
added a new property to USB DT node for this purpose.
Modified host driver to make use of the information passed
through DT to
Kindly ignore this.
I would send another patch updating device tree binding directly with the new
proposed property.
-Original Message-
From: devicetree-discuss [mailto:devicetree-discuss-
bounces+vakul=freescale@lists.ozlabs.org] On Behalf Of Vakul Garg
Sent: Friday, December
This patch is tested in ARM:exynos5250 with LPAE enabled. The coherent_dma_mask
needs to be defined to DMA_BIT_MASK(64) as dma-mapping API's check it against
64-bit mask.
Signed-off-by: Subash Patel subash...@samsung.com
---
drivers/of/platform.c |2 +-
1 files changed, 1 insertions(+), 1
Does it mean that pci is supposed be always 64 bit wide?
And there is no option to have just 32bit values.
I certainly believe that all PCIe (not PCI) transfers are
nominally multiples of 64bit data.
There are (effectively) 8 byte-lane enables to allow partial word
transfers (I'm not sure
AIC family of audio CODECs from TI features a programmable miniDSP for
performing signal processing operations. Due to commonality of functions
across the CODECs a common library will be used to provide support for them.
Signed-off-by: Mehar Bajwa mehar.ba...@ti.com
---
sound/soc/codecs/Kconfig
Hi Linus,
Le 11/12/2012 01:28, Linus Walleij a écrit :
On Mon, Dec 10, 2012 at 11:08 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC
On Mon, Dec 10, 2012 at 1:27 AM, Inki Dae inki@samsung.com wrote:
2012/12/10 Stéphane Marchesin stephane.marche...@gmail.com
On Sun, Dec 9, 2012 at 10:26 PM, Inki Dae inki@samsung.com wrote:
2012/12/6 R. Chandrasekar rcse...@samsung.com
From: R. Chandrasekar
On Mon, Dec 3, 2012 at 1:41 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
IGEP technology devices are TI OMAP3 SoC based industrial embedded
and computer-on-module boards. This patch-set adds initial device
tree support for these devices.
The device trees allows to boot
On Wed, Dec 12, 2012 at 11:11 AM, Benoit Cousson b-cous...@ti.com wrote:
Hi Javier,
On 12/12/2012 09:25 AM, Javier Martinez Canillas wrote:
On Mon, Dec 3, 2012 at 1:41 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
IGEP technology devices are TI OMAP3 SoC based
On Wed, Dec 12, 2012 at 10:49 AM, Grant Likely wrote:
On Wed, Dec 12, 2012 at 10:37 AM, Michal Simek
mon...@monstr.eumailto:mon...@monstr.eu wrote:
On 12/10/2012 10:41 PM, Grant Likely wrote:
drivers/pci/pci-of.c would be good. I'd also accept drivers/of/pci.c
which might actually be a
DT bindings for PCI host bridges often use the ranges property to describe
memory and IO ranges - this binding tends to be the same across architectures
yet several parsing implementations exist, e.g. arch/mips/pci/pci.c,
arch/powerpc/kernel/pci-common.c, arch/sparc/kernel/pci.c and
On Wed, Dec 12, 2012 at 01:34:24PM +, Thierry Reding wrote:
On Wed, Dec 12, 2012 at 12:19:12PM +, Andrew Murray wrote:
I've been working on a relatively architecture agnostic PCI host bridge
driver
and also wanted to avoid duplicating more generic DT parsing code for PCI
Hello Kumar
This has been applied to:
git://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git.
Regards
Vakul
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Thursday, December 13, 2012 3:00 AM
To: Garg Vakul-B16394
Cc:
On Thu, Dec 13, 2012 at 09:13:33AM +, Thierry Reding wrote:
Hi Andrew,
I don't like iterator interfaces too much, but I can live with that.
Other than that the patch looks good to me and I'll try to work it into
my Tegra PCIe patch series.
Just two minor comments below.
diff --git
On Thu, Dec 13, 2012 at 10:03:18AM +, Thierry Reding wrote:
On Thu, Dec 13, 2012 at 09:45:43AM +, Andrew Murray wrote:
On Thu, Dec 13, 2012 at 09:13:33AM +, Thierry Reding wrote:
Hi Andrew,
I don't like iterator interfaces too much, but I can live with that.
Other than
The configuration change building ipmi_si into the kernel precludes the
use of a custom driver that can utilize more than one KCS interface,
multiple IPMBs, and more than one BMC. This capability is important for
fault-tolerant systems.
Even if the kernel option ipmi_si.trydefaults=0 is
Tegra USB host driver is using port instance number,
to handle some of the hardware issues on SOC e.g. reset PORT0
twice etc. As instance number based handling looks ugly,
making use of information passed through DT for achieving this.
Signed-off-by: Venu Byravarasu vbyravar...@nvidia.com
---
As Tegra USB host driver is using instance number for resetting
PORT0 twice, adding a new DT property for handling this.
Signed-off-by: Venu Byravarasu vbyravar...@nvidia.com
---
.../bindings/usb/nvidia,tegra20-ehci.txt |2 ++
arch/arm/boot/dts/tegra20.dtsi |
On 12/14/2012 10:25 AM, Evans, Robert wrote:
Corey,
Thanks for the thoughtful reply. Below I respond in detail to
these three points.
1) Why building a variant kernel with ipmi_si as a module is not
feasible.
2) User mode access to IPMI on Stratus systems (e.g. ipmitool).
3) ipmi_si hot
RHEL builds the ipmi_si into the kernel by default, rather than as a
module, because it is required early in order to be available for ACPI
opregion access. However, it appears that some of our customers have
custom ipmi drivers, and this gets in their way.
Stratus is currently evaluating your
Corey,
Thanks for the thoughtful reply. Below I respond in detail to
these three points.
1) Why building a variant kernel with ipmi_si as a module is not
feasible.
2) User mode access to IPMI on Stratus systems (e.g. ipmitool).
3) ipmi_si hot removal seems to not work as needed.
Stratus
The aims of this series are:
* Add DT bindings to to INTC
* Allowing sh7372 and r8a7740 ARM shmobile SoCs to use DT
to initialise INTCA
Key Changes since v5 (previous public revision of this series)
* Drop support for sh73a0 SoC.
To be useful this requires a fuller initialisation than jsut
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Add information of device node to struct intc_desc.
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
v7
* Delete
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
This provides OF support of SH/INTC.
The SH/INTC driver is used by SuperH and ARM/SH-MOBILE.
At the moment, SuperH does not have the plan corresponding to DT.
DT of SH/INTC has taken the form where the table data of the C
is managed by DT,
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
This CPU has three interrupt controllers (INTCA and INTCA IRQ pins).
This supports these.
NOTE: This supports DT of INTCA only.
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
This CPU has four interrupt controllers (INTCA, pins-High and pins-Low).
This supports these.
Note: This supports DT of INTCA only.
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/boot/dts/sh7372.dtsi | 784 +
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/boot/dts/r8a7740.dtsi | 743 +++-
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/mach-shmobile/setup-r8a7740.c |2 +-
1 file changed, 1
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/boot/dts/r8a7740-armadillo800eva.dts |2 +-
1 file changed, 1
This is in preparation for initialising INTC using DT.
The proposed INTC configuration is not complete and does
not allow the TMU to be initialised, to exclude it when using DT.
Cc: Magnus Damm d...@opensource.se
Cc: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/mach-shmobile/setup-sh7372.c |2 +-
1 file changed, 1
Add scu.txt under arm for ARM Snoop Control Unit(SCU)
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
Documentation/devicetree/bindings/arm/scu.txt | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/scu.txt
diff --git
Add Snoop Control Unit(SCU) node for Cortex A9 MP.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/boot/dts/tegra30.dtsip |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
index 8feba6d..84a41c2 100644
---
Add Snoop Control Unit(SCU) node for Cortex A9 MP.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/boot/dts/tegra20.dtsip |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 3e046b1..d325aed 100644
---
Set Snoop Control Unit(SCU) register base address dynamically from DT.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/mach-tegra/platsmp.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-tegra/platsmp.c
Nvidia's Tegra has multiple uart controller which supports:
- APB dma based controller fifo read/write.
- End Of Data interrupt in incoming data to know whether end
of frame achieve or not.
- Hw controlled RTS and CTS flow control to reduce SW overhead.
Add serial driver to use all above
On Tue, Dec 11, 2012 at 8:01 PM, Inki Dae inki@samsung.com wrote:
2012/12/12 Stéphane Marchesin stephane.marche...@gmail.com
On Mon, Dec 10, 2012 at 1:27 AM, Inki Dae inki@samsung.com wrote:
2012/12/10 Stéphane Marchesin stephane.marche...@gmail.com
On Sun, Dec 9, 2012 at
On 12/14/2012 12:02 PM, Corey Minyard wrote:
On 12/14/2012 10:25 AM, Evans, Robert wrote:
Corey,
Thanks for the thoughtful reply. Below I respond in detail to
these three points.
1) Why building a variant kernel with ipmi_si as a module is not
feasible.
2) User mode access to IPMI on
The aims of this series are:
* Add DT bindings to to INTC
* Allowing sh7372 and r8a7740 ARM shmobile SoCs to use DT
to initialise INTCA
Change since v7
* Squash the first and second patch of the series and rename there result
SH: intc: Add support OF for INTC
Changes v5 and v7 (v6 was not
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
This provides OF support of SH/INTC.
The SH/INTC driver is used by SuperH and ARM/SH-MOBILE.
At the moment, SuperH does not have the plan corresponding to DT.
DT of SH/INTC has taken the form where the table data of the C
is managed by DT,
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
This CPU has three interrupt controllers (INTCA and INTCA IRQ pins).
This supports these.
NOTE: This supports DT of INTCA only.
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
This CPU has four interrupt controllers (INTCA, pins-High and pins-Low).
This supports these.
Note: This supports DT of INTCA only.
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/boot/dts/sh7372.dtsi | 784 +
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/boot/dts/r8a7740-armadillo800eva.dts |2 +-
1 file changed, 1
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/mach-shmobile/setup-r8a7740.c |2 +-
1 file changed, 1
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/boot/dts/r8a7740.dtsi | 743 +++-
This is in preparation for initialising INTC using DT.
The proposed INTC configuration is not complete and does
not allow the TMU to be initialised, to exclude it when using DT.
Cc: Magnus Damm d...@opensource.se
Cc: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Cc: Magnus Damm d...@opensource.se
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Simon Horman horms+rene...@verge.net.au
---
arch/arm/mach-shmobile/setup-sh7372.c |2 +-
1 file changed, 1
Nvidia's Tegra has multiple uart controller which supports:
- APB dma based controller fifo read/write.
- End Of Data interrupt in incoming data to know whether end
of frame achieve or not.
- Hw controlled RTS and CTS flow control to reduce SW overhead.
Add serial driver to use all above
Hi Rob,
Rob Herring robherri...@gmail.com wrote @ Mon, 17 Dec 2012 15:00:46 +0100:
On 12/17/2012 12:18 AM, Hiroshi Doyu wrote:
Set Snoop Control Unit(SCU) register base address dynamically from DT.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/mach-tegra/platsmp.c | 23
Rob Herring robherri...@gmail.com wrote @ Tue, 18 Dec 2012 14:46:36 +0100:
On 12/18/2012 03:21 AM, Hiroshi Doyu wrote:
Hi Rob,
Rob Herring robherri...@gmail.com wrote @ Mon, 17 Dec 2012 15:00:46 +0100:
On 12/17/2012 12:18 AM, Hiroshi Doyu wrote:
Set Snoop Control Unit(SCU) register
This RFC is aimed at introducing CoreSight framework as well as
individual CoreSight trace component drivers adhering to ARM
CoreSight specification. Some prior discussion on this can be
referred at [1].
There are 3 kinds of CoreSight trace components:
* Sources: Responsible for producing trace
Hiroshi Doyu hd...@nvidia.com wrote @ Tue, 18 Dec 2012 17:15:46 +0200 (EET):
Rob Herring robherri...@gmail.com wrote @ Tue, 18 Dec 2012 14:46:36 +0100:
On 12/18/2012 03:21 AM, Hiroshi Doyu wrote:
Hi Rob,
Rob Herring robherri...@gmail.com wrote @ Mon, 17 Dec 2012 15:00:46
+0100:
From: Pratik Patel prat...@codeaurora.org
CoreSight components are compliant with the ARM CoreSight
architecture specification and can be connected in various
topologies to suite a particular SoCs tracing needs. These trace
components can generally be classified as sources, links and
sinks. Trace
From: Pratik Patel prat...@codeaurora.org
This driver manages CoreSight TMC (Trace Memory Controller) which
can act as a link or a sink depending upon its configuration. It
can present itself as an ETF (Embedded Trace FIFO) or ETR
(Embedded Trace Router).
ETF when configured in circular buffer
From: Pratik Patel prat...@codeaurora.org
This driver manages CoreSight TPIU (Trace Port Interface Unit)
which acts as a sink. TPIU is typically connected to some offchip
hardware hosting a storage buffer.
Signed-off-by: Pratik Patel prat...@codeaurora.org
---
drivers/coresight/Makefile
From: Pratik Patel prat...@codeaurora.org
This driver manages CoreSight ETB (Embedded Trace Buffer) which
acts as a circular buffer sink collecting generated trace data.
Signed-off-by: Pratik Patel prat...@codeaurora.org
---
drivers/coresight/Makefile|2 +-
From: Pratik Patel prat...@codeaurora.org
This driver manages CoreSight Funnel which acts as a link.
Funnels have multiple input ports (typically 8) each of which
represents an input trace data stream. These multiple input trace
data streams are interleaved into a single output stream coming
out
From: Pratik Patel prat...@codeaurora.org
This driver manages CoreSight STM (System Trace Macrocell) and
provides apis and user interface to support software
instrumentation based tracing that takes advantage of the STM
hardware.
Signed-off-by: Pratik Patel prat...@codeaurora.org
---
From: Pratik Patel prat...@codeaurora.org
This driver manages CoreSight Replicator that takes single input
trace data stream and replicates it to produce two identical
trace data output streams. Replicators are typically used to
route single interleaved trace data stream to two or more sinks.
NVIDIA's Tegra has multiple UART controller which supports:
- APB DMA based controller fifo read/write.
- End Of Data interrupt in incoming data to know whether end
of frame achieve or not.
- HW controlled RTS and CTS flow control to reduce SW overhead.
Add serial driver to use all above
On Thu, 6 Dec 2012 14:55:41 -0800, Stepan Moskovchenko
step...@codeaurora.org wrote:
In some situations, userspace may want to resolve a
device by function and logical number (ie, serial0)
rather than by the base address or full device path. Being
able to resolve a device by alias frees
Hi Peter,
Thanks for this work. Comments below...
On Wed, 12 Dec 2012 10:04:52 +0100, Peter Ujfalusi peter.ujfal...@ti.com
wrote:
Support for device tree booted kernel.
For usage see:
Documentation/devicetree/bindings/leds/leds-pwm.txt
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Hi Pratik,
On Tue, Dec 18, 2012 at 07:19:17PM +, prat...@codeaurora.org wrote:
This RFC is aimed at introducing CoreSight framework as well as
individual CoreSight trace component drivers adhering to ARM
CoreSight specification. Some prior discussion on this can be
referred at [1].
On Fri, 14 Dec 2012 11:20:53 +0530, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
The arbitrator is a general purpose function which uses two GPIOs to
communicate with another device to claim/release a bus.
i2c_transfer()
if adapter-gpio_arbit
i2c_bus_claim();
On Fri, 14 Dec 2012 11:05:12 -0800, Allen Martin amar...@nvidia.com wrote:
Fix name of slink binding and address of sflash example to make it
self consistent.
Change-Id: Ia89c3017c958bdf670036caf516eabce6f893096
Applied, thanks.
g.
Signed-off-by: Allen Martin amar...@nvidia.com
---
On Fri, 14 Dec 2012 14:58:14 -0700, Jason Gunthorpe
jguntho...@obsidianresearch.com wrote:
On Fri, Dec 14, 2012 at 08:26:29PM +, Grant Likely wrote:
If the soc_devices are getting triggered on that and they shouldn't be,
then we need a mechanism in the soc_bridge node to kick out
On Fri, 14 Dec 2012 17:43:31 -0800, Dmitry Torokhov dmitry.torok...@gmail.com
wrote:
On Saturday, December 15, 2012 01:13:45 AM Grant Likely wrote:
On Wed, 12 Dec 2012 13:33:48 -0800, Simon Glass s...@chromium.org wrote:
Use the key-matrix layer to interpret key scan information from the EC
On Mon, 17 Dec 2012 12:17:16 -1000, Mitch Bradley w...@firmworks.com wrote:
On 12/17/2012 12:04 PM, Stephen Warren wrote:
On 12/17/2012 02:58 PM, Mitch Bradley wrote:
On 12/17/2012 11:36 AM, Stephen Warren wrote:
On 12/17/2012 05:10 AM, Laxman Dewangan wrote:
Nvidia's Tegra has multiple
On Mon, 17 Dec 2012 14:31:34 -0700, Stephen Warren swar...@wwwdotorg.org
wrote:
On 12/17/2012 10:10 AM, Grant Likely wrote:
On Mon, 17 Dec 2012 17:40:49 +0530, Laxman Dewangan ldewan...@nvidia.com
wrote:
Nvidia's Tegra has multiple uart controller which supports:
- APB dma based
On Tue, 18 Dec 2012 07:04:15 +0100, Jean-Christophe PLAGNIOL-VILLARD
plagn...@jcrosoft.com wrote:
On 21:19 Wed 28 Nov , Jean-Christophe PLAGNIOL-VILLARD wrote:
On 13:59 Mon 26 Nov , Grant Likely wrote:
On Wed, 21 Nov 2012 11:14:08 +0100, Jean-Christophe PLAGNIOL-VILLARD
On Tue, 18 Dec 2012 11:32:03 +0100, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
As the function just returns the np-full_name or the string no-node, the
passed device_node pointer is not changed in any way.
The passed parameter can therefore be a const pointer.
Also, fix the
On Sat, 15 Dec 2012 00:27:58 +, Grant Likely grant.lik...@secretlab.ca
wrote:
On Tue, 11 Dec 2012 16:20:39 -0500, Murali Karicheri m-kariche...@ti.com
wrote:
This adds OF support to DaVinci SPI controller to configure platform
data through device bindings. Also replaces clk_enable()
On Thu, 13 Dec 2012 16:12:53 +0530, Padmavathi Venna padm...@samsung.com
wrote:
Add support for device based discovery.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 75 +++
sound/soc/samsung/dma.c
Hi Sylwester,
On Wed, Dec 19, 2012 at 11:05 AM, Vivek Gautam
gautamvivek1...@gmail.com wrote:
CC: Doug Anderson
On Wed, Dec 19, 2012 at 4:49 AM, Sylwester Nawrocki
sylvester.nawro...@gmail.com wrote:
Hi Vivek,
On 12/18/2012 02:56 PM, Vivek Gautam wrote:
Adding support to parse device
CC: Doug Anderson
On Sat, Dec 15, 2012 at 12:50 PM, Grant Likely
grant.lik...@secretlab.ca wrote:
On Thu, 13 Dec 2012 20:22:26 +0530, Vivek Gautam gautam.vi...@samsung.com
wrote:
Using chip specific compatible string as it should be.
So fixing this for ehci-s5p, ohci-exynos and dwc3-exynos
CC: Doug Anderson
On Thu, Dec 13, 2012 at 9:39 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
On Thu, Dec 13, 2012 at 8:22 PM, Vivek Gautam gautam.vi...@samsung.com
wrote:
Using specific chip in compatible strings. Newer SOCs can claim
device by using older string in the compatible list.
CC: Doug Anderson
On Thu, Dec 13, 2012 at 9:40 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
CC: LKML
On Thu, Dec 13, 2012 at 8:22 PM, Vivek Gautam gautam.vi...@samsung.com
wrote:
Using specific chip in compatible strings. Newer SOCs can claim
device by using older string in the
On 12/19/2012 05:02 AM, Grant Likely wrote:
On Wed, Dec 19, 2012 at 10:58 AM, Grant Likely
grant.lik...@secretlab.ca wrote:
Commit 50c8af4cf9, of: introduce for_each_matching_node_and_match()
renamed of_find_matching_node() to of_find_matching_node_and_match() and
created a new static inline
CC: Doug Anderson
On Sat, Dec 15, 2012 at 12:53 PM, Grant Likely
grant.lik...@secretlab.ca wrote:
On Thu, 13 Dec 2012 22:06:01 +0530, Vivek Gautam gautam.vi...@samsung.com
wrote:
Adding EHCI device tree node for Exynos5250 along with
the device base adress and gpio line for vbus.
CC: Doug Anderson
On Thu, Dec 13, 2012 at 10:17 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
Adding DWC3 device tree node for Exynos5250 along with the
device address and clock support needed for the controller.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
Changes from v2:
NVIDIA's Tegra has multiple UART controller which supports:
- APB DMA based controller fifo read/write.
- End Of Data interrupt in incoming data to know whether end
of frame achieve or not.
- HW controlled RTS and CTS flow control to reduce SW overhead.
Add serial driver to use all above
On Wed, 19 Dec 2012 07:50:00 -0600, Rob Herring robherri...@gmail.com wrote:
On 12/19/2012 05:02 AM, Grant Likely wrote:
On Wed, Dec 19, 2012 at 10:58 AM, Grant Likely
grant.lik...@secretlab.ca wrote:
Commit 50c8af4cf9, of: introduce for_each_matching_node_and_match()
renamed
On 12/15/2012 07:27 AM, Jonas Gorski wrote:
Fixes the following warning:
include/linux/of_platform.h:106:13: warning: 'struct device' declared inside
parameter list [enabled by default]
include/linux/of_platform.h:106:13: warning: its scope is only this
definition or declaration, which is
On 19 December 2012 16:12, Rob Herring robherri...@gmail.com wrote:
On 12/15/2012 07:27 AM, Jonas Gorski wrote:
Fixes the following warning:
include/linux/of_platform.h:106:13: warning: 'struct device' declared inside
parameter list [enabled by default]
include/linux/of_platform.h:106:13:
Mehar == Mehar Bajwa mehar.ba...@ti.com writes:
Hi,
Mehar TI TLV320AIC3262 is a flexible, low-power, low-voltage stereo
Mehar audio codec with digital microphone inputs and programmable
Mehar outputs. It includes powertune capabilities, enhanced
Mehar fully-programmable miniDSP, fixed
On 12/19/2012 03:58 AM, Grant Likely wrote:
Commit 50c8af4cf9, of: introduce for_each_matching_node_and_match()
renamed of_find_matching_node() to of_find_matching_node_and_match() and
created a new static inline of_find_matching_node() wrapper around the
new name. However, the change
On 12/19/2012 07:15 AM, Laxman Dewangan wrote:
On Wednesday 19 December 2012 06:31 PM, Grant Likely wrote:
On Mon, 17 Dec 2012 14:31:34 -0700, Stephen
Warrenswar...@wwwdotorg.org wrote:
On 12/17/2012 10:10 AM, Grant Likely wrote:
On Mon, 17 Dec 2012 17:40:49 +0530, Laxman
On 12/19/2012 05:23 AM, Will Deacon wrote:
Hi Pratik,
On Tue, Dec 18, 2012 at 07:19:17PM +, prat...@codeaurora.org wrote:
This RFC is aimed at introducing CoreSight framework as well as
individual CoreSight trace component drivers adhering to ARM
CoreSight specification. Some prior
On Wed, Dec 19, 2012 at 01:24:14PM +, Grant Likely wrote:
On Thu, 13 Dec 2012 16:12:53 +0530, Padmavathi Venna padm...@samsung.com
wrote:
+- compatible : samsung,samsung-i2s
Isn't that kind of redundant? :-)
The format of the compatible strings should be vendor,part-number-i2s.
Hi Vinod,
On 11/15/2012 07:37 PM, Vinod Koul wrote:
On Fri, 2012-11-09 at 14:01 -0600, Jon Hunter wrote:
Hi Vinod,
A few people have been asking me if getting device-tree support for DMA
engine is plan for record for v3.8. I know that you were working through
implementing a common interface
On Wed, Dec 19, 2012 at 12:32:01PM +, Grant Likely wrote:
I'm not convinced on the design of this protocol. It won't scale beyond
2 bus masters and it seems very specific to the design of a specific
piece of hardware. I don't think it is mature enough to bake into the
I ought to point out
On Wed, Dec 19, 2012 at 12:57:22PM +, Grant Likely wrote:
On Fri, 14 Dec 2012 17:43:31 -0800, Dmitry Torokhov
dmitry.torok...@gmail.com wrote:
On Saturday, December 15, 2012 01:13:45 AM Grant Likely wrote:
On Wed, 12 Dec 2012 13:33:48 -0800, Simon Glass s...@chromium.org wrote:
Use
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