Hi all,
So, lets see if i have all this right.
IO space needs to stay where it is, somewhere in the top 1GB, because
it is limited to the 32bit address space.
We must have some SDRAM in the bottom of the 40bit address range in
order that DMA works. Bounce buffers are used for anything which is
On Thursday 21 March 2013, Lior Amsalem wrote:
From: Jason Gunthorpe [mailto:jguntho...@obsidianresearch.com]
Sent: Thursday, March 21, 2013 11:46 PM
On Thu, Mar 21, 2013 at 11:35:21PM +0200, Lior Amsalem wrote:
*) It would require Linux to change the internal registers address
On Fri, Mar 22, 2013 at 11:23:32, Nori, Sekhar wrote:
On 3/21/2013 1:31 PM, Philip, Avinash wrote:
On Wed, Mar 20, 2013 at 18:17:59, Peter Korsgaard wrote:
Sekhar == Sekhar Nori nsek...@ti.com writes:
Sekhar On 3/20/2013 12:11 PM, Philip Avinash wrote:
Add da850 EHRPWM ECAP DT node.
From: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
This will allow to use gpio for chip select with no modification in the
driver binding
When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased.
On Thu, Mar 21, 2013 at 04:06:25PM +, Thomas Petazzoni wrote:
Dear Andrew Murray,
On Fri, 1 Mar 2013 12:23:36 +, Andrew Murray wrote:
This patch factors out common implementations patterns to reduce overall
kernel
code and provide a means for host bridge drivers to directly
Andrew,
On Fri, 22 Mar 2013 09:39:36 +, Andrew Murray wrote:
Thanks, I've tested this successfully with the Marvell PCIe driver. I'm
about to send a new version of the Marvell PCIe patch set that includes
this RFC proposal.
I only made two small changes compared to your version,
On Thursday 21 March 2013, Jason Gunthorpe wrote:
On Thu, Mar 21, 2013 at 10:15:23PM +0100, Thomas Petazzoni wrote:
Dear Jason Gunthorpe,
*) It only works when LPAE is enabled, so we would have to have
different internal register addresses depending on whether LPAE is
enabled
On Thu, Mar 21, 2013 at 05:30:09PM +, Thomas Petazzoni wrote:
From: Andrew Murray andrew.mur...@arm.com
This patch factors out common implementations patterns to reduce overall
kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's
On Thu, Mar 21, 2013 at 06:30:09PM +0100, Thomas Petazzoni wrote:
From: Andrew Murray andrew.mur...@arm.com
This patch factors out common implementations patterns to reduce overall
kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's
On Fri, 22 Mar 2013 11:12:39 +0100, Thierry Reding wrote:
This sounds like you're trying to do too much within the for loop. When
we discussed this previously I had a vague idea that this functionality
could be wrapped into something a bit more object-like.
What I had in mind was something
On Thu, Mar 21, 2013 at 8:07 PM, Grant Likely grant.lik...@secretlab.ca wrote:
On Thu, Mar 21, 2013 at 12:52 PM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Thu, 2013-03-21 at 11:24 +, Grant Likely wrote:
kexec comes to mind (all 4 variants of fs2dt.c (yuck !)), dtc, various
On Fri, Mar 22, 2013 at 10:20:59AM +, Thomas Petazzoni wrote:
On Fri, 22 Mar 2013 11:12:39 +0100, Thierry Reding wrote:
This sounds like you're trying to do too much within the for loop. When
we discussed this previously I had a vague idea that this functionality
could be wrapped
On Thu, Mar 21, 2013 at 05:26:15PM +0100, Gregory CLEMENT wrote:
From: Lior Amsalem al...@marvell.com
For mvebu IOs are 32 bits and we have 40 bits memory due to LPAE so
make sure we give 32 bits addresses to the IOs.
Signed-off-by: Lior Amsalem al...@marvell.com
Tested-by: Franklin
On Thu, Mar 21, 2013 at 09:31:01PM -0500, Rob Herring wrote:
Perhaps re-writing it like this would be more clear:
if (irq_num == 2){
__sp804_clockevents_init(base + TIMER_2_BASE, irq, clk1, name);
__sp804_clocksource_and_sched_clock_init(base, name, clk0, 1);
} else {
This is the eight version of the Tegra114 clockframework. It is based on the
next-20130320-fixed branch of
git://nv-tegra.nvidia.com/user/swarren/linux-2.6.git,
http://patchwork.ozlabs.org/patch/229972/ and
http://patchwork.ozlabs.org/patch/229978/
It has been boottested on Dalmore and
tegra_boot_secondary() relies on some of the car ops. This means having an
uninitialized tegra_cpu_car_ops will lead to an early boot panic.
Providing a dummy struct avoids this and makes adding Tegra114 clock support
in a bisectable way a lot easier.
Signed-off-by: Peter De Schrijver
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
*
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |2 ++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 12
drivers/clk/tegra/clk.h |2 ++
2 files changed, 10 insertions(+), 4
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 38 --
Hi,
2013/3/20 Philipp Zabel p.za...@pengutronix.de:
This patch adds three exported functions to lib/genalloc.c:
devm_gen_pool_create, dev_get_gen_pool, and of_get_named_gen_pool.
devm_gen_pool_create is a managed version of gen_pool_create that keeps
track of the pool via devres and allows
2013/3/20 Philipp Zabel p.za...@pengutronix.de:
This driver requests and remaps a memory region as configured in the
device tree. It serves memory from this region via the genalloc API.
It optionally enables the SRAM clock.
Other drivers can retrieve the genalloc pool from a phandle pointing
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |6 +++---
drivers/clk/tegra/clk-tegra20.c | 20
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 839 +++
drivers/clk/tegra/clk.h | 50 +++-
Hi Andrew,
2013/3/20 Philipp Zabel p.za...@pengutronix.de:
Hi, last time I posted was a bit close to the merge window, so I'm
reposting now. Greg, Arnd, could you take the first two patches?
These patches add support to configure on-chip SRAM via device-tree
node or platform data and to
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-periph.c | 11 ++-
drivers/clk/tegra/clk-tegra20.c |
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-periph-gate.c |9 +
drivers/clk/tegra/clk.h |2 ++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
.../bindings/clock/nvidia,tegra114-car.txt | 317
1 files changed, 317 insertions(+), 0 deletions(-)
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk.c |1 +
drivers/clk/tegra/clk.h |7 +++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a6f2fa6..2a8e424 100644
---
Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
On Tue, Mar 12, 2013 at 08:46:12PM -0700, Simon Glass wrote:
Hi,
On Fri, Feb 15, 2013 at 2:49 PM, Simon Glass s...@chromium.org wrote:
Given a set of nodes and properties, find the regions of the device tree
which describe those parts.
A test is provided which builds a tree while
Hi Hector,
Le 21/03/2013 17:57, Hector Palacios a écrit :
On 03/07/2013 02:06 PM, Maxime Ripard wrote:
Hi Hector,
Le 06/03/2013 18:02, Hector Palacios a écrit :
I'm creating the DT for a custom platform based on Freescale MX28 CPU
and I have some doubts about where to add some pin mux
Hi all,
This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
instead of rolling its own implementation. As a result, all users of this
mv643xx_eth driver are converted to register an orion-mdio platform_device.
The mvmdio driver is also updated to support an interrupt line
This patch enhances the mvmdio to support a SMI error/done interrupt
line which can be used along with a wait queue instead of doing
busy-waiting on the registers. This is a feature which is available in
the mv643xx_eth SMI code and thus reduces again the gap between the two.
Signed-off-by:
This patch changes the mvmdio driver not to use device tree
helper functions such as of_mdiobus_register() and of_iomap() so we can
instantiate this driver using a classic platform_device approach. Use
the device manager helper to ioremap() the base register cookie so we
get automatic freeing upon
This patch renames the base register cookie in the mvmdio drive from
smireg to regs since a subsequent patch is going to use an ioremap()
cookie whose size is larger than a single register of 4 bytes. No
functionnal code change introduced.
Acked-by: Thomas Petazzoni
This patch converts the Marvell MV643XX ethernet driver to use the
Marvell Orion MDIO driver. As a result, PowerPC and ARM platforms
registering the Marvell MV643XX ethernet driver are also updated to
register a Marvell Orion MDIO driver. This driver voluntarily overlaps
with the Marvell Ethernet
of_phy_connect is useful for most systems, but some drivers will want
finer-grained control over their PHYs, and won't want to use the
PHY Lib state machine or interrupt handlers.
This mirrors phy_attach() in libphy, which is already exported.
Signed-off-by: Andy Fleming aflem...@freescale.com
Hello,
On Fri, 22 Mar 2013 14:39:24 +0100, Florian Fainelli wrote:
Hi all,
This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
instead of rolling its own implementation. As a result, all users of this
mv643xx_eth driver are converted to register an orion-mdio
This patch series adds support for DRM FIMD DT for Exynos4 DT Machines,
specifically for Exynos4412 SoC.
changes since v8:
- addressed comments to add missing documentation for clock and
clock-names
properties as pointed out by Sachin Kamat sachin.ka...@linaro.org
changes since
Adds common FIMD device node for all Exynos4 SoCs.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
arch/arm/boot/dts/exynos4.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 9ac47d5..2480aaa
Adds FIMD DT support to Origen quad board
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
arch/arm/boot/dts/exynos4412-origen.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
Adds FIMD DT binding documentation for both Samsung SoC and Board, with an
example
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
.../devicetree/bindings/video/samsung-fimd.txt | 68
1 file changed, 68 insertions(+)
create mode 100644
Hi Guennadi,
On Wed, Mar 20, 2013 at 08:40:15PM +0100, Guennadi Liakhovetski wrote:
Hi all
On Sat, 2 Mar 2013, Mark Brown wrote:
On Mon, Feb 18, 2013 at 10:57:44AM +0100, Guennadi Liakhovetski wrote:
Add device-tree bindings to the AS3711 regulator and backlight drivers.
On Fri, Mar 22, 2013 at 02:39:24PM +0100, Florian Fainelli wrote:
Hi all,
This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
instead of rolling its own implementation. As a result, all users of this
mv643xx_eth driver are converted to register an orion-mdio
Le 03/22/13 15:14, Jason Cooper a écrit :
On Fri, Mar 22, 2013 at 02:39:24PM +0100, Florian Fainelli wrote:
Hi all,
This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
instead of rolling its own implementation. As a result, all users of this
mv643xx_eth driver are
From: Florian Fainelli flor...@openwrt.org
Date: Fri, 22 Mar 2013 14:39:24 +0100
This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
instead of rolling its own implementation. As a result, all users of this
mv643xx_eth driver are converted to register an orion-mdio
Quoting Kukjin Kim (2013-03-21 16:26:24)
Mike Turquette wrote:
[...]
Furthermore if I *had* agreed on the previous version it would still
have been appropriate to put my Acked-by on those patches, which is
clearly missing today.
BTW, how about following?
On Fri, Mar 22, 2013 at 03:24:55PM +0100, Florian Fainelli wrote:
Le 03/22/13 15:14, Jason Cooper a écrit :
On Fri, Mar 22, 2013 at 02:39:24PM +0100, Florian Fainelli wrote:
Hi all,
This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
instead of rolling its own
Le 03/22/13 15:29, Jason Cooper a écrit :
Ok, thanks! Does that mean that you want these changes to go via
your tree? David initially applied my v2 of this patchset, and since
it thouches mostly ethernet driver stuff, I would rather make it go
via his tree if both of you agree.
Yeah, I thought
This patch allows to use a different regulator than LDO9 as TSIREF.
It also only turns on the regulator when there are actual measurements
to be done. It is not needed for pen detection.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/mfd/da9052-i2c.txt |
On 03/22/2013 02:10 AM, Linus Walleij wrote:
On Fri, Mar 15, 2013 at 12:21 PM, Javier Martinez Canillas
martinez.jav...@gmail.com wrote:
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 159f5c5..f5feb43 100644
--- a/drivers/gpio/gpio-omap.c
+++
Hi Fabio,
thank you for the comments.
Am Freitag, den 22.03.2013, 12:51 -0300 schrieb Fabio Estevam:
Philipp Zabel wrote:
if (!tsi-stopped) {
+ error = regulator_enable(tsi-tsiref);
+ if (error 0) {
+ dev_err(tsi-da9052-dev,
+
On Friday, March 22, 2013 12:51:23 PM Fabio Estevam wrote:
Philipp Zabel wrote:
if (!tsi-stopped) {
+ error = regulator_enable(tsi-tsiref);
+ if (error 0) {
+ dev_err(tsi-da9052-dev,
+ Failed to enable TSIREF
This is just a split of the previous version of this patch(-set), no code
changes.
Guennadi Liakhovetski (3):
mfd: as3711: add OF support
regulator: as3711: add OF support
backlight: as3711: add OF support
Documentation/devicetree/bindings/mfd/as3711.txt | 73 +
Add support for configuring AS3711 backlight driver from DT.
Signed-off-by: Guennadi Liakhovetski g.liakhovetski+rene...@gmail.com
Reviwed-by: Mark Brown broo...@opensource.wolfsonmicro.com
---
drivers/video/backlight/as3711_bl.c | 118 ++-
1 files changed, 117
Add Flat Device Tree support to the AS3711 MFD driver. This patch just
allows to bind the driver to I2C devices, instantiated from the DT.
DT support for AS3711 cell drivers will be added in separate drivers.
Signed-off-by: Guennadi Liakhovetski g.liakhovetski+rene...@gmail.com
Reviwed-by: Mark
AS3711 regulator OF support only evaluates standard regulator DT
properties.
Signed-off-by: Guennadi Liakhovetski g.liakhovetski+rene...@gmail.com
Reviwed-by: Mark Brown broo...@opensource.wolfsonmicro.com
---
drivers/regulator/as3711-regulator.c | 74 -
1 files
Hi Guennadi,
On Fri, Mar 22, 2013 at 05:15:47PM +0100, Guennadi Liakhovetski wrote:
Add Flat Device Tree support to the AS3711 MFD driver. This patch just
allows to bind the driver to I2C devices, instantiated from the DT.
DT support for AS3711 cell drivers will be added in separate drivers.
Hi,
On Tue, Mar 12 2013, Tony Prisk wrote:
On Mon, 2013-03-11 at 22:36 +0800, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
The variable 'mmc' is initialized but never used
otherwise, so remove the unused variable.
Signed-off-by: Wei Yongjun
On Thu, Mar 07, 2013 at 11:54:03PM +0100, Michael Grzeschik wrote:
Hey Alex,
On Thu, Jan 24, 2013 at 11:42:53AM +0200, Alexander Shishkin wrote:
Peter Chen peter.c...@freescale.com writes:
On Tue, Nov 27, 2012 at 05:16:55PM +0100, Michael Grzeschik wrote:
Nearly every SoC from
On 03/21/2013 07:47 AM, Laxman Dewangan wrote:
This series add the regulators for Dalmore platform.
Dalmore also have the Palma PMIC as primary PMIC but
dt population will be send later once DT documentation
finalize.
The series is applied. The first 3 patches to Tegra's for-3.10/dt
branch,
On Fri, Mar 22, 2013 at 07:28:54AM +0100, Andrew Lunn wrote:
IO space needs to stay where it is, somewhere in the top 1GB, because
it is limited to the 32bit address space.
Yes
We must have some SDRAM in the bottom of the 40bit address range in
order that DMA works. Bounce buffers are used
As suggested by Rob Herring move back to get the parent releationship from dt
like in the first versions, but set the handler from the interrupt property
rather than from a specific list.
This version also implements (hopefully correctly) an idea from him and
Arnd Bergmann to have the parent
This move is necessary to make use of the irqchip infrastructure
for the following devicetree support for s3c24xx architectures.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/mach-s3c24xx/Makefile |2 +-
drivers/irqchip/Makefile |
Might be confusing for people to read the code without having the
datasheet nearby.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/irqchip/irq-s3c24xx.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-s3c24xx.c
The list in used was from the s3c2450, a close cousin of the s3c2416.
As it's not possible to distinguish between the s3c2416 and s3c2450
the additional interrupts of the s3c2450 will only be available thru
devicetree later.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Enables post-init setting of the desired typehandler for the interrupt.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/irqchip/irq-s3c24xx.c | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/irqchip/irq-s3c24xx.c
Add the necessary code to initialize the interrupt controller
thru devicetree data using the irqchip infrastructure.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
.../interrupt-controller/samsung,s3c24xx-irq.txt | 64 +++
drivers/irqchip/irq-s3c24xx.c | 181
On Friday 22 March 2013, Jason Gunthorpe wrote:
At a certain point low mem exhaustion becomes a serious issue for
Linux, a system that can't DMA to 85% of its memory is incredibly
broken, IMHO.
A lot of workloads will also suffer from lowmem exhaustion even without
the DMA zone problem. If
This patch adds support for registering DSA switches using Device Tree
bindings. Note that we support programming the switch routing table even
though no in-tree user seems to require it. I tested this on Armada 370
with a Marvell 88E6172 (not supported by mainline yet).
Signed-off-by: Florian
On Friday 22 March 2013, Heiko Stübner wrote:
+ interrupt-controller@4a00 {
+ compatible = samsung,s3c24xx-irq;
+ reg = 0x4a00 0x100;
+ interrupt-controller;
+
+ intc:intc {
+ interrupt-controller;
+
On Friday 22 March 2013, Heiko Stübner wrote:
As suggested by Rob Herring move back to get the parent releationship from dt
like in the first versions, but set the handler from the interrupt property
rather than from a specific list.
This version also implements (hopefully correctly) an idea
Am Freitag, 22. März 2013, 22:04:54 schrieb Arnd Bergmann:
On Friday 22 March 2013, Heiko Stübner wrote:
As suggested by Rob Herring move back to get the parent releationship
from dt like in the first versions, but set the handler from the
interrupt property rather than from a specific
Am Freitag, 22. März 2013, 21:55:57 schrieb Arnd Bergmann:
On Friday 22 March 2013, Heiko Stübner wrote:
+ interrupt-controller@4a00 {
+ compatible = samsung,s3c24xx-irq;
+ reg = 0x4a00 0x100;
+ interrupt-controller;
+
+ intc:intc {
On Fri, 22 Mar 2013, Mark Brown wrote:
On Fri, Mar 22, 2013 at 05:15:48PM +0100, Guennadi Liakhovetski wrote:
AS3711 regulator OF support only evaluates standard regulator DT
properties.
It looks like this has no dependencies on the MFD patch, is that
correct?
Yes, that's correct. That
On Friday 22 March 2013, Heiko Stübner wrote:
Not all main interrupts are parent interrupts, so it would be difficult to
distinguish between main interrupts that are a parent and the ones that are
not - is a -1 a valid cell-value for interrupts?
I'm actually not sure if negative numbers are
On 03/22/2013 10:33 AM, Stephen Warren wrote:
On 03/22/2013 02:10 AM, Linus Walleij wrote:
On Fri, Mar 15, 2013 at 12:21 PM, Javier Martinez Canillas
martinez.jav...@gmail.com wrote:
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 159f5c5..f5feb43 100644
---
On Fri, Mar 22, 2013 at 7:29 PM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Fri, 2013-03-22 at 13:03 -0500, Nathan Fontenot wrote:
We don't ever free old property values, mainly I assume since we don't keep
reference counts and can't know when it is safe to do so. The problem I
From: Andrew Murray andrew.mur...@arm.com
This patch factors out common implementations patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This
From: Thierry Reding thierry.red...@avionic-design.de
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
Signed-off-by: Jingoo Han jg1@samsung.com
---
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
As agreed by the community, PCI host drivers will now be stored in
drivers/pci/host. This commit adds this directory and the related
Kconfig/Makefile changes to allow new drivers to be added in this
directory.
Signed-off-by: Thomas
Exynos5440 has a PCIe controller which can be used as Root Complex.
This driver supports a PCIe controller as Root Complex mode.
Signed-off-by: Surendranath Gurivireddy Balla suren.re...@samsung.com
Signed-off-by: Siva Reddy Kallam siva.kal...@samsung.com
Signed-off-by: Jingoo Han
Enable PCIe support for Exynos5440 which has two PCIe controllers.
Signed-off-by: Jingoo Han jg1@samsung.com
---
arch/arm/Kconfig |1 +
arch/arm/mach-exynos/Kconfig |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
Exynos5440 has two PCIe controllers which can be used as root complex
for PCIe interface.
Signed-off-by: Jingoo Han jg1@samsung.com
---
arch/arm/boot/dts/exynos5440-ssdk5440.dts |8 +++
arch/arm/boot/dts/exynos5440.dtsi | 32 +
2 files changed,
This patch adds an of_property_read_u32_index() function to allow
reading a single indexed u32 value from a property containing multiple
u32 values.
Signed-off-by: Tony Prisk li...@prisktech.co.nz
---
cc: Grant Likely grant.lik...@secretlab.ca
cc: Rob Herring rob.herr...@calxeda.com
cc:
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