Hi,
On Monday 25 March 2013 03:16 PM, Laxman Dewangan wrote:
On Monday 25 March 2013 03:02 PM, Kishon Vijay Abraham I wrote:
From: Graeme Gregory g...@slimlogic.co.uk
This is the driver for the OTG transceiver built into the Palmas chip. It
handles the various USB OTG events that can be
Hi Arnd,
thanks again for taking the time to look at the changes.
Am Montag, 25. März 2013, 23:00:46 schrieb Arnd Bergmann:
On Monday 25 March 2013, Heiko Stübner wrote:
Add the necessary code to initialize the interrupt controller
thru devicetree data using the irqchip infrastructure.
On Mon, 25 Mar 2013, Linus Walleij wrote:
On Mon, Mar 25, 2013 at 5:46 PM, Lee Jones lee.jo...@linaro.org wrote:
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
prcmu-tcpm);
if (!res) {
-
On Tue, Mar 26, 2013 at 9:17 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 25 Mar 2013, Linus Walleij wrote:
On Mon, Mar 25, 2013 at 5:46 PM, Lee Jones lee.jo...@linaro.org wrote:
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.
It was ok at the time of the support of only the A10 and A13 that
looks pretty much the same, but it's beginning to be troublesome with
the future
During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.
It was ok at the time of the support of only the A10 and A13 that
looks pretty much the same, but it's beginning to be troublesome with
the future
The Allwinner sun6i (A31) has a slightly different watchdog, that
doesn't allow to use the already existing restart code.
Rework a bit the restart code to allow to plug in more easily different
restart handlers depending on the device tree.
In the past, we were also meaning sunxi as a generic
On Tuesday 26 March 2013 02:31 PM, Graeme Gregory wrote:
On 26/03/13 06:03, Kishon Vijay Abraham I wrote:
+static int palmas_usb_read(struct palmas *palmas, unsigned int reg,
+ unsigned int *dest)
+{
+ unsigned int addr;
+ int slave;
+
+ slave =
On Fri, Mar 15, 2013 at 2:31 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
The binding documentation for the OMAP GPIO controller has the
#interrupt-cells property listed before #interrupt-controller
property but its description after.
This is confusing so we move
On Tuesday 26 March 2013 02:57 PM, Graeme Gregory wrote:
On 26/03/13 09:12, Laxman Dewangan wrote:
On Tuesday 26 March 2013 02:31 PM, Graeme Gregory wrote:
But still you are using the PALMAS macro here and indirectly it is
tied up. It is not completely independent.
If need to be independent
On Tue, 26 Mar 2013, Linus Walleij wrote:
On Tue, Mar 26, 2013 at 9:17 AM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 25 Mar 2013, Linus Walleij wrote:
On Mon, Mar 25, 2013 at 5:46 PM, Lee Jones lee.jo...@linaro.org wrote:
res = platform_get_resource_byname(pdev,
Register a device tree clock provider for the clocks
on the OMAP4 SoC. Also provide the binding information.
For now we only provide AUXCLKs.
Signed-off-by: Roger Quadros rog...@ti.com
---
.../devicetree/bindings/clock/omap4-clock.txt | 33
arch/arm/boot/dts/omap4.dtsi
On Tuesday 26 March 2013 03:51 PM, Felipe Balbi wrote:
* PGP Signed by an unknown key
Hi,
On Tue, Mar 26, 2013 at 09:01:42AM +, Graeme Gregory wrote:
From: Graeme Gregory g...@slimlogic.co.uk
This is the driver for the OTG transceiver built into the Palmas
chip. It
handles the various
On 25/03/13 14:29, Sascha Hauer wrote:
Put it differently. OpenBSD might have much better clock support.
Imagine it can dynamically figure out the correct esdhc frequencies
for different usecases on the fly. In this situation it would be
counterproductive if Linux requires static values for
On Tuesday 26 March 2013 03:21 PM, Graeme Gregory wrote:
On 26/03/13 09:34, Laxman Dewangan wrote:
Kishon,
I think it is very much possible. You can pass the interrupt throough
IRQ_RESOURCE and populate it from DT. If you provide proper interrupt
parent and irq number then irq framework take
Fixes some typos in the documentation of exynos-adc.txt.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
.../devicetree/bindings/arm/samsung/exynos-adc.txt |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Michael Grzeschik m...@pengutronix.de writes:
Hi Alexander, Fabio, Greg,
On Mon, Mar 25, 2013 at 10:11:15AM -0300, Fabio Estevam wrote:
Hi Alexander,
On Thu, Jan 24, 2013 at 7:42 AM, Alexander Shishkin
alexander.shish...@linux.intel.com wrote:
Peter Chen peter.c...@freescale.com writes:
Hi,
On Tue, Mar 26, 2013 at 03:58:41PM +0530, Laxman Dewangan wrote:
On Tuesday 26 March 2013 03:51 PM, Felipe Balbi wrote:
* PGP Signed by an unknown key
Hi,
On Tue, Mar 26, 2013 at 09:01:42AM +, Graeme Gregory wrote:
From: Graeme Gregory g...@slimlogic.co.uk
This is the driver
Hi,
On Tue, Mar 26, 2013 at 02:08:05PM +0200, Alexander Shishkin wrote:
http://git.pengutronix.de/git/mgr/linux.git v3.9/topic/usb-phy
4414a59 Merge 'v3.9/topic/usb-phy' into usb-3.9
a806027 usb: otg: mxs-phy: remove clkgate/sftrst clearing
026881b usb: otg: mxs-phy: Improve mxs phy
Michael Grzeschik m...@pengutronix.de writes:
Hi Alexander, Fabio, Greg,
Some more fun:
/*
* Peters branch already contain the usbmisc series,
* but they never made it to ci-for-greg, although
* Alexander already mentioned (24 Jan 2013) to queue them.
*/
Greg KH gre...@linuxfoundation.org writes:
Ugh, this is getting to be a horrible mess.
Alexander, what is going on here? You can't just constantly ignore
patches, that's reserved for kernel developers with more experience :)
Long story short, I'm waiting for a coherent set of patches to
This patch adds device tree node for the SYSREG registers block
found in Samsung S5P/Exynos SoC series. The SYSREG module
generates control signals for the ARM CPU and various IP blocks
and buses. SYSREG block registers are exposed through APB bus
interface. A sysreg device tree node is to be
On 03/26/2013 04:51 AM, Viresh Kumar wrote:
big LITTLE is ARM's new Architecture focussing power/performance needs of
modern
world. More information about big LITTLE can be found here:
http://www.arm.com/products/processors/technologies/biglittleprocessing.php
Hi Alexander,
On Tue, Mar 26, 2013 at 02:29:40PM +0200, Alexander Shishkin wrote:
Michael Grzeschik m...@pengutronix.de writes:
Some more fun:
/*
* Peters branch already contain the usbmisc series,
* but they never made it to ci-for-greg, although
* Alexander already mentioned (24
Hi Javier,
On 03/26/2013 10:33 AM, Javier Martinez Canillas wrote:
On Fri, Mar 15, 2013 at 2:31 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
The binding documentation for the OMAP GPIO controller has the
#interrupt-cells property listed before #interrupt-controller
From: Steffen Trumtrar s.trumt...@pengutronix.de
Add ldb device tree node and clock lookups.
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx6q.dtsi | 17 +
arch/arm/boot/dts/imx6qdl.dtsi |
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx51.dtsi| 2 ++
arch/arm/boot/dts/imx53.dtsi| 2 ++
arch/arm/mach-imx/clk-imx51-imx53.c | 7 ---
3 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/imx51.dtsi
The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk.h | 17
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx53.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 7a6f5a8..b07bbdcc 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++
So it can be used in clk-imx6q.c for revision dependent clock tree setup.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-imx6q.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/common.h
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx51-imx53.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx53.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index b07bbdcc..30aed40 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++
On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 5 +
1
From: Sascha Hauer s.ha...@pengutronix.de
This adds support for the LVDS Display Bridge contained
in i.MX5 and i.MX6 SoCs.
Bit mapping, data width, and video timings are configurable
via device tree. Dual-channel mode is supported for a single
high-resolution source.
Signed-off-by: Sascha Hauer
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/clk-imx6q.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git
Hi,
the following patches add support for LVDS displays on
i.MX53 and i.MX6q boards.
The clock patches are needed because the LVDS serial clock
has to be in lockstep with the IPU display interface clock
providing the pixel data. A fixed factor of 7:1 (or 3.5:1 in
dual link mode) needs to be
On 03/26/2013 03:10 PM, Benoit Cousson wrote:
Hi Javier,
On 03/26/2013 10:33 AM, Javier Martinez Canillas wrote:
On Fri, Mar 15, 2013 at 2:31 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
The binding documentation for the OMAP GPIO controller has the
#interrupt-cells
On 26 March 2013 18:47, Rob Herring robherri...@gmail.com wrote:
On 03/26/2013 04:51 AM, Viresh Kumar wrote:
I fail to see anything bL specific here. This is just multi-cluster, but
even for that I don't see anything new other than simply allowing per
cpu or per cluster opp's. The fact that we
On 03/26/2013 03:29 PM, Benoit Cousson wrote:
On 03/26/2013 03:10 PM, Benoit Cousson wrote:
Hi Javier,
On 03/26/2013 10:33 AM, Javier Martinez Canillas wrote:
On Fri, Mar 15, 2013 at 2:31 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
The binding documentation for the
Hi Thomas,
Am Dienstag, den 26.03.2013, 15:34 +0100 schrieb Thomas Petazzoni:
Dear Philipp Zabel,
On Tue, 26 Mar 2013 15:13:56 +0100, Philipp Zabel wrote:
+/*
+ * For a device declaring compatible = fsl,imx6q-ldb, fsl,imx53-ldb,
+ * of_match_device will walk through this list and take
From: Guennadi Liakhovetski g.liakhovet...@gmx.de
This patch adds a document describing common OF bindings for video
capture, output and video processing devices. It is curently mainly
focused on video capture devices, with data busses defined by
standards such as ITU-R BT.656 or MIPI-CSI2.
It
Hello,
I've written a watchdog driver for simple chips that are connected via
GPIO. Driver can be used with chips from different manufacturers.
Should compatible property be set to gpio-wdt or
generic,gpio-wdt? Are there any other problems with following
bindings?
-
Required properties:
On 03/26/2013 04:28 AM, Laxman Dewangan wrote:
On Tuesday 26 March 2013 03:51 PM, Felipe Balbi wrote:
On Tue, Mar 26, 2013 at 09:01:42AM +, Graeme Gregory wrote:
...
+ return regmap_read(palmas-regmap[slave], addr, dest);
Please use the generic api for palmas_read()/palmas_write(0
Hello,
This series of patches introduces PCIe support for the Marvell Armada
370 and Armada XP. In the future, we plan to extend the driver to
cover Kirkwood platforms, and possibly other Marvell EBU platforms as
well.
As we are approaching 3.10, I would now like to get formal Acked-by,
or
From: Andrew Murray andrew.mur...@arm.com
This patch factors out common implementations patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This
From: Thierry Reding thierry.red...@avionic-design.de
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry
From: Thierry Reding thierry.red...@avionic-design.de
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
---
drivers/of/of_pci.c| 25 +
As agreed by the community, PCI host drivers will now be stored in
drivers/pci/host. This commit adds this directory and the related
Kconfig/Makefile changes to allow new drivers to be added in this
directory.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc:
The current revision of the datasheet only mentions the gatable clocks
for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
interfaces. After confirmation with Marvell engineers, this patch adds
the missing gatable clocks for
Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
necessary Device Tree informations to make these interfaces availabel.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi | 45 +
1 file
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can
be used to plug mini-PCIe devices. We therefore enable the PCIe
interface that corresponds to this slot.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
units (two 4x or quad 1x and two 4x/1x). We therefore add the
necessary Device Tree
The Globalscale Mirabox platform uses one PCIe interface for an
available mini-PCIe slot, and the other PCIe interface for an internal
USB 3.0 controller. We add the necessary Device Tree informations to
enable those two interfaces.
Signed-off-by: Thomas Petazzoni
The Marvell evaluation board (DB) for the Armada XP SoC has 6
physicals full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-db.dts | 33
The Marvell evaluation board (DB) for the Armada 370 SoC has 2
physical full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 17 +
1
Now that we have the necessary drivers and Device Tree informations to
support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI
option.
Also, since the Armada 370 Mirabox has a built-in USB XHCI controller
connected on the PCIe bus, enable the corresponding options as well.
Signed-off-by:
The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so
we enable the corresponding PCIe interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-gp.dts | 21 +
1 file changed, 21
This patch factors out common implementation patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This will make it easier to write archiecture
On 03/26/2013 03:27 AM, Graeme Gregory wrote:
...
If we are tightly coupling as above then using platform_irq is an extra
inefficiency. You both have to populate this then parse it afterwards.
Why not just use the regmap helper? Ill admit this code is like this as
there was a period where
On Tuesday 26 March 2013, Thomas Petazzoni wrote:
This series of patches introduces PCIe support for the Marvell Armada
370 and Armada XP. In the future, we plan to extend the driver to
cover Kirkwood platforms, and possibly other Marvell EBU platforms as
well.
As we are approaching 3.10, I
On Tue, Mar 26, 2013 at 05:18:32PM +0100, Thomas Petazzoni wrote:
+ pcie-controller {
+ compatible = marvell,armada-370-pcie;
+ status = disabled;
+ device_type = pci;
+
+ #address-cells = 3;
+
On 11 March 2013 12:24, Kukjin Kim kgene@samsung.com wrote:
Sachin Kamat wrote:
Hi Kukjin,
Can you please look into this series as it is pending since quite some time.
Applied, I have another opinion about the compatible string though...
Couldn't find this series in your latest
Changes in this iteration include mostly adaptation to changes at the
V4L2 OF parser lib and an addition of clocks/clock-names properties
in the bindings of the IP blocks.
If there is no more comments I intend to send a pull request including
the DT bindings documentation, the V4L2 OF parser and
This patch support for binding the driver to the MIPI-CSIS
devices instantiated from device tree and parsing the SoC
and board specific properties. The MIPI CSI-2 channel is
determined by the value of reg property placed in csis'
port subnode.
Signed-off-by: Sylwester Nawrocki
This patch adds device tree support for FIMC driver on S5PV210
and Exynos4 SoCs.
The FIMC IP block's features and quirks encoded statically in
the driver are now parsed from the device tree. Once all relevant
platforms are converted to device tree based booting the FIMC
variant data structures
This patch adds the device tree support for FIMC-LITE device
driver. The bindings include compatible property for the Exynos5
SoC series, however the actual implementation for these SoCs will
be added in a separate patch.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by:
Before the camera ports can be used the pinmux needs to be configured
properly. This patch adds a function to set the camera ports pinctrl
to a default state within the media driver's probe().
The camera port(s) are then configured for the video bus operation.
Signed-off-by: Sylwester Nawrocki
On 03/26/2013 05:39 PM, Sylwester Nawrocki wrote:
Changes in this iteration include mostly adaptation to changes at the
V4L2 OF parser lib and an addition of clocks/clock-names properties
in the bindings of the IP blocks.
If there is no more comments I intend to send a pull request including
Hello,
This set of patches introduces Message Signaled Interrupt support in
the Marvell EBU PCIe driver. It has been successfully tested on the
Armada XP GP platform and the Armada 370 DB platform with an Intel
e1000e PCIe network card that supports MSI.
This is based on work done by Lior
In preparation for moving the IRQ controller driver to
drivers/irqchip/, we don't want the IRQ controller driver to be
responsible for initializing the L2 cache. Instead, let's initialize
the L2 cache at the init_early() level, like mach-exynos/common.c is
doing.
Signed-off-by: Thomas Petazzoni
When the Marvell Armada 370/XP support was included in the kernel, the
drivers/irqchip/ directory didn't exist and the minimal infrastructure
in it also didn't exist. Now that we have those things in place, we
move the Armada 370/XP IRQ controller driver from
If we move the IRQ handler function above the initialization function,
we avoid a forward declaration. This wasn't done as part of the
previous commit, in order to increase the readibility of the previous
commit, who was also moving the IRQ controller driver from arch/arm to
drivers/irqchip.
In preparation for the introduction of MSI support in the IRQ
controller driver, we clarify the implementation of IPI using
additional defines for the manipulation of doorbells. Just like IPIs
are implemented using doorbells, MSIs will also use doorbells, so it
makes sense to do this preparatory
The mpic alias is already defined in the common armada-370-xp.dtsi, so
there's no need to repeat it at the armada-xp.dtsi and armada-370.dtsi
level. Moreover, we're going to slightly change how the interrupt
controller is declared in the common armada-370-xp.dtsi file.
Signed-off-by: Thomas
This commit introduces the support for the MSI interrupts in the
armada-370-xp interrupt controller driver. It registers an IRQ domain
associated with the 'msi' node in the Device Tree, which the PCI
controller will refer to in a followup commit.
The MSI interrupts use the 16 high doorbells, and
In the Marvell hardware, MSI interrupts are supported using doorbells,
and those doorbells are handled through registers that are part of the
registers managed by the IRQ controller driver: they are the same
registers used for handling IPI interrupts. Therefore, it is clearly
the responsability of
From: Thierry Reding thierry.red...@avionic-design.de
The new struct msi_chip is used to associated an MSI controller with a
PCI bus. It is automatically handed down from the root to its children
during bus enumeration.
This patch provides default (weak) implementations for the architecture-
This commit adds the MSI support for the Marvell EBU PCIe driver. The
driver now looks at the 'msi-parent' property of the PCIe controller
DT node, and if it exists, it gets the associated IRQ domain, which
should be the MSI interrupt controller registered by the IRQ
controller driver.
Using
Now that the Marvell EBU PCIe driver supports MSI, we can adjust the
Device Tree for the Armada 370 and Armada XP SoCs so that the PCIe
controller nodes point to the MSI interrupt controller using the
'msi-parent' property.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
Now that MSI support is available, both in the IRQ controller driver
and in the PCIe driver, let's enable it in the mvebu_defconfig used
for Armada 370/XP platforms.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/configs/mvebu_defconfig |1 +
1 file changed,
On Tuesday 26 March 2013, Thomas Petazzoni wrote:
@@ -72,6 +73,10 @@ void __init armada_370_xp_init_early(void)
ARMADA_370_XP_MBUS_WINS_SIZE,
ARMADA_370_XP_SDRAM_WINS_BASE,
ARMADA_370_XP_SDRAM_WINS_SIZE);
+
+#ifdef
On Tuesday 26 March 2013, Thomas Petazzoni wrote:
When the Marvell Armada 370/XP support was included in the kernel, the
drivers/irqchip/ directory didn't exist and the minimal infrastructure
in it also didn't exist. Now that we have those things in place, we
move the Armada 370/XP IRQ
Dear Jason Gunthorpe,
On Tue, 26 Mar 2013 10:34:21 -0600, Jason Gunthorpe wrote:
On Tue, Mar 26, 2013 at 05:18:32PM +0100, Thomas Petazzoni wrote:
+ pcie-controller {
+ compatible = marvell,armada-370-pcie;
+ status = disabled;
+
Dear Arnd Bergmann,
On Tue, 26 Mar 2013 16:53:48 +, Arnd Bergmann wrote:
On Tuesday 26 March 2013, Thomas Petazzoni wrote:
@@ -72,6 +73,10 @@ void __init armada_370_xp_init_early(void)
ARMADA_370_XP_MBUS_WINS_SIZE,
Hello,
On Tue, 26 Mar 2013 17:52:15 +0100, Thomas Petazzoni wrote:
This set of patches introduces Message Signaled Interrupt support in
the Marvell EBU PCIe driver. It has been successfully tested on the
Armada XP GP platform and the Armada 370 DB platform with an Intel
e1000e PCIe network
On Tuesday 26 March 2013, Thomas Petazzoni wrote:
+ mpic: main-intc@d002 {
+#interrupt-cells = 1;
+interrupt-controller;
+ };
+
+ msi: msi-intc@d002 {
+#interrupt-cells = 1;
+
Dear Arnd Bergmann,
On Tue, 26 Mar 2013 17:07:41 +, Arnd Bergmann wrote:
I think the @d002 part needs to be removed for the nodes that
have no reg property.
Sure, will fix.
I think I did not follow the entire discussion. What has led to having
two subnodes in the end, rather than a
On Tuesday 26 March 2013, Thomas Petazzoni wrote:
To the readers of LAKML: the mailing list software has, for some
reason, decided that all the e-mails in this series had a Suspicious
header. They have all been generated by git format-patch and sent with
git send-email, just like the previous
Dear Arnd Bergmann,
On Tue, 26 Mar 2013 17:18:08 +, Arnd Bergmann wrote:
The mailing list rejects patches that have an in-reply-to header with
pointing to a different subject as the new email.
It also has an exception for emails that have the work PATCH in
brackets, but not [RFC] or [GIT
On Tue, Mar 26, 2013 at 05:52:22PM +0100, Thomas Petazzoni wrote:
This commit introduces the support for the MSI interrupts in the
armada-370-xp interrupt controller driver. It registers an IRQ domain
associated with the 'msi' node in the Device Tree, which the PCI
controller will refer to in
On Tuesday 26 March 2013, Thomas Petazzoni wrote:
I've tried to explain that in the commit log of PATCH 6, which says:
However, we need the driver to expose two different IRQ domains: one
for the main interrupt controller itself, and one for the MSI
interrupt controller. In
On Tue, Mar 26, 2013 at 04:16:10PM +, Grant Likely wrote:
On Tue, 8 Jan 2013 12:10:20 +0200, Pantelis Antoniou
pa...@antoniou-consulting.com wrote:
Hi Lee,
On Jan 8, 2013, at 12:00 PM, Lee Jones wrote:
At the end of the line, some kind of hardware glue is going to be
On Tue, Mar 26, 2013 at 10:34:21AM -0600, Jason Gunthorpe wrote:
[...]
This basically looks fine to me, however, I think it is valuable if
you and Thierry could use the same method to pass per-port registers. I
expect others are going to reference these bindings for future work,
and one
On 03/26/2013 10:57 AM, Graeme Gregory wrote:
On 26/03/13 16:22, Stephen Warren wrote:
On 03/26/2013 03:27 AM, Graeme Gregory wrote:
...
If we are tightly coupling as above then using platform_irq is an extra
inefficiency. You both have to populate this then parse it afterwards.
Why not just
Wolfram,
On Wed, Mar 13, 2013 at 9:36 AM, Doug Anderson diand...@chromium.org wrote:
The i2c-arbitrator-cros-ec driver implements the arbitration scheme
that the Embedded Controller (EC) on the ARM Chromebook expects to use
for bus multimastering. This i2c-arbitrator-cros-ec driver could also
Dear Arnd Bergmann,
On Tue, 26 Mar 2013 18:38:22 +, Arnd Bergmann wrote:
Note that both the parent and the child node need to have the
'interrupt-controller' empty property:
* The interrupt-controller property is needed in the main
interrupt controller node
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