Thomas Abraham wrote:
>
> This patch series allows device tree enabled platforms to setup a runtime
> I/O mapping for the chip-id controller. This helps to remove statically
> defined I/O mapping for the Chip-ID controller.
>
> Thomas Abraham (2):
> ARM: Exynos: Create virtual I/O mapping for C
Hi Kukjin,
On Fri, Mar 15, 2013 at 1:32 PM, Vivek Gautam wrote:
> This patch-set is in continuation with patch-series:
> [PATCH v4 0/4] Enable ehci, ohci and dwc3 devices on exynos5250
> out of which follwowing patches have been picked up:
> ARM: Exynos5250: Enabling ehci-s5p driver
> ARM: Exyno
Hi Kukjin,
On Fri, Mar 15, 2013 at 1:26 PM, Vivek Gautam wrote:
> Based on 'for-next' of linux-samsung tree with following patches
> from Doug on top:
> usb: Document clocks in samsung, exynos4210-ehci/ohci bindings
> ARM: dts: add usb 2.0 clock references to exynos5250 device tree
>
> Also depe
Added clock entry definitions to MFC bindings document.
Signed-off-by: Sachin Kamat
---
.../devicetree/bindings/media/s5p-mfc.txt |5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt
b/Documentation/devicetree/bindings/media/s5
Added MFC related clock entries in exynos4.dtsi file.
Signed-off-by: Sachin Kamat
---
Based on Kukjin's for-next.
Dependent on the below patch:
https://patchwork.kernel.org/patch/2349361/
---
arch/arm/boot/dts/exynos4.dtsi |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dt
Jingoo Han wrote:
>
> On Friday, March 15, 2013 8:01 AM, Doug Anderson wrote:
> >
> > The exynox4210-ehci and exynos4210-ohci nodes need a clock specified
> > using the common clock framework. Document it.
> >
> > Signed-off-by: Doug Anderson
>
> It looks good.
> Acked-by: Jingoo Han
>
>
App
Tushar Behera wrote:
>
> Arndale board support has been updated using pin-control and
> common clock framework.
>
> The patchset is based on Kukjin's for-next.
> commit d58f6a153f40 ("Merge branch 'next/clk-exynos-2' into for-next")
>
> It depends on following patchset.
>
> [PATCH 0/2] ARM: dts
Hi Tony,
On Thursday 04 April 2013 05:12 AM, Tony Lindgren wrote:
> Hi,
>
[]..
>> @@ -1663,6 +1664,40 @@ static struct omap_clk omap44xx_clks[] = {
>> CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
>> };
>>
>> +static struct clk *scrm_clks[] = {
>> +&auxclk0_ck,
>> +&a
On Wed, Apr 03, 2013 at 11:18:57AM +0200, Guennadi Liakhovetski wrote:
> Hi
>
> This 2 patches add DT irqpin support on marzen-reference. Only
> compile-tested due to the lack of hardware. The patches can go
> independently via their respective trees. irqpin on marzen will not work
> if patch 2
A simple frame-buffer describes a raw memory region that may be rendered
to, with the assumption that the display hardware has already been set
up to scan out from that buffer.
This is useful in cases where a bootloader exists and has set up the
display hardware, but a Linux driver doesn't yet exi
On 04/03/2013 12:46 AM, Olof Johansson wrote:
> On Wed, Apr 03, 2013 at 12:17:10AM -0600, Stephen Warren wrote:
>> A dumb frame-buffer describes a raw memory region that may be rendered
>> to, with the assumption that the display hardware has already been set
>> up to scan out from that buffer.
>>
On Wednesday, March 27, 2013 10:04 PM, Thierry Reding wrote:
>
> On Tue, Mar 26, 2013 at 04:20:23PM +, Andrew Murray wrote:
> > This patch factors out common implementation patterns to reduce overall
> > kernel
> > code and provide a means for host bridge drivers to directly obtain struct
> >
On 04/03/2013 06:53 AM, Kishon Vijay Abraham I wrote:
> The PHY framework provides a set of APIs for the PHY drivers to
> create/destroy a PHY and APIs for the PHY users to obtain a reference to the
> PHY with or without using phandle. To obtain a reference to the PHY without
> using phandle, the p
Hi,
* Roger Quadros [130319 07:31]:
> Register a device tree clock provider for AUX clocks
> on the OMAP4 SoC. Also provide the binding information.
>
> Signed-off-by: Roger Quadros
> ---
> .../devicetree/bindings/clock/omap4-clock.txt | 32 ++
> arch/arm/boot/dts/omap4.
On 04/03/2013 06:53 AM, Kishon Vijay Abraham I wrote:
> Added a generic PHY framework that provides a set of APIs for the PHY drivers
> to create/destroy a PHY and APIs for the PHY users to obtain a reference to
> the PHY with or without using phandle. To obtain a reference to the PHY
> without usi
From: Stephen Warren
The ARM GIC binding defines a few custom cells and flags for its IRQ
specifier. Provide names for those.
Signed-off-by: Stephen Warren
---
v2: No change.
v1: Moved header. Added include guard.
(this patch was previously posted separately, hence there are
changes in
From: Stephen Warren
Many IRQ device tree bindings use the same flags. Create a header to
define those.
Signed-off-by: Stephen Warren
---
v2: No change.
v1: Moved header. Added include guard.
(this patch was previously posted separately, hence there are
changes in v1!)
---
include/dt-b
From: Stephen Warren
Many GPIO device tree bindings use the same flags. Create a header to
define those.
Signed-off-by: Stephen Warren
---
v2: No change.
v1: Moved header. Added include guard.
(this patch was previously posted separately, hence there are
changes in v1!)
---
include/dt-
From: Stephen Warren
Replace cmd_dtc with cmd_dtc_cpp, and delete the latter.
Previously, a special file extension (.dtsp) was required to trigger
the C pre-processor to run on device tree files. This was ugly. Now that
previous changes have enhanced cmd_dtc_cpp to collect dependency
information
From: Stephen Warren
Prior to this change, when compiling *.dts to *.dtb, the dependency
output from dtc would be used, and when compiling *.dtsp to *.dtb, the
dependency output from gcc -E alone would be used, despite dtc also
being invoked (on a temporary file that was guaranteed to have no
dep
From: Stephen Warren
The current use-case for fixdep is: a source file is run through a single
processing step, which creates a single dependency file as a side-effect,
which fixdep transforms into the file used by the kernel build process.
In order to transparently run the C pre-processor on de
From: Stephen Warren
The recent dtc+cpp support allows header files and C pre-processor
defines/macros to be used when compiling device tree files. These
headers will typically define various constants that are part of the
device tree bindings.
The original patch which set up the dtc+cpp include
On 04/03/2013 12:27 PM, Stephen Warren wrote:
> On 04/03/2013 11:52 AM, Stephen Warren wrote:
>> On 04/03/2013 08:40 AM, Peter De Schrijver wrote:
>>> This is the nineth version of the Tegra114 clockframework. It is based on
>>> the
>>> next-20130320-fixed branch of
>>> git://nv-tegra.nvidia.com/u
On 04/03/2013 02:53 PM, Kishon Vijay Abraham I wrote:
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-bindings.txt
@@ -0,0 +1,67 @@
+This document explains only the dt data binding. For general information about
s/dt data/device tree ?
+PHY subsystem refer Documentation/phy.txt
On Thu, Mar 14, 2013 at 3:14 PM, Christian Daudt wrote:
> - Adds a module to provide calls into secure monitor mode
> - Uses this module to make secure monitor calls to enable L2 cache.
>
> Updates from V1:
> - Split DT portion into separate patch
> - replace #ifdef-ed L2 code with "if".
> - move
On 03/19/2013 01:51 PM, Stephen Warren wrote:
> On 03/18/2013 06:29 AM, Venu Byravarasu wrote:
>> As part of this series, apart from patch containing changes to register TEGRA
>> USB PHY driver as platform driver, prepared below patches:
>> 1. Re-arranging & adding new DT properties.
>> 2. Getting
On 03/19/2013 01:53 PM, Stephen Warren wrote:
> On 03/18/2013 06:29 AM, Venu Byravarasu wrote:
>> This patch updates all Tegra board files so that they contain all the
>> properties required by the updated USB DT binding. Note that this patch
>> only adds the new properties and does not yet remove
On 03/19/2013 02:10 PM, Stephen Warren wrote:
> On 03/18/2013 06:29 AM, Venu Byravarasu wrote:
>> Check return values from all GPIO APIs and handle errors accordingly.
>
>> Remove clk_disable_unprepare which is no more needed.
>
> The call to clk_disable_unprepare is incorrect in the current code
* Tony Lindgren [130403 11:42]:
> * Stephen Warren [130403 09:49]:
> > On 04/03/2013 03:16 AM, Prabhakar Lad wrote:
> > > Hi Linus/Stephen,
> > >
> > > I am working adding DT nodes for DA850.
> > >
> > > Following is the pin control snippet of da850.dtsi:-
> > >
> > > pmx_core: pinm
On 04/02/2013 02:25 PM, Markus Mayer wrote:
> Hi all,
>
> I have a few questions regarding the implementation of the of_iomap()
> function.
>
> As it currently stands, the function parses the device tree for the
> device's address and then simply calls ioremap() with that address and
> the associ
* Stephen Warren [130403 09:49]:
> On 04/03/2013 03:16 AM, Prabhakar Lad wrote:
> > Hi Linus/Stephen,
> >
> > I am working adding DT nodes for DA850.
> >
> > Following is the pin control snippet of da850.dtsi:-
> >
> > pmx_core: pinmux@1c14120 {
> ...
> > i2
On 04/03/2013 11:52 AM, Stephen Warren wrote:
> On 04/03/2013 08:40 AM, Peter De Schrijver wrote:
>> This is the nineth version of the Tegra114 clockframework. It is based on the
>> next-20130320-fixed branch of
>> git://nv-tegra.nvidia.com/user/swarren/linux-2.6.git,
... [it depends on]
>> http://
On 04/03/2013 08:40 AM, Peter De Schrijver wrote:
> Signed-off-by: Peter De Schrijver
I see this patch does depend on my "clk: tegra: defer application of
init table", although my patch was based on top of this series so needs
to be adjusted to remove the Tegra114 portions so it can be applied fi
On 04/03/2013 08:40 AM, Peter De Schrijver wrote:
> This is the nineth version of the Tegra114 clockframework. It is based on the
> next-20130320-fixed branch of
> git://nv-tegra.nvidia.com/user/swarren/linux-2.6.git,
That's not a particularly useful base; these patches won't be applied to
linux-n
On 04/03/2013 08:40 AM, Peter De Schrijver wrote:
> The device tree binding models Tegra114 CAR (Clock And Reset) as a single
> monolithic clock provider.
> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
> b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car
On Wed, Apr 03, 2013 at 09:06:40PM +0800, Wei Yongjun wrote:
> From: Wei Yongjun
>
> Fix to return a negative error code from the error handling
> case instead of 0, as returned elsewhere in this function.
Applied, thanks.
signature.asc
Description: Digital signature
__
On 04/03/2013 03:16 AM, Prabhakar Lad wrote:
> Hi Linus/Stephen,
>
> I am working adding DT nodes for DA850.
>
> Following is the pin control snippet of da850.dtsi:-
>
> pmx_core: pinmux@1c14120 {
...
> i2c0_pins: pinmux_i2c0_pins {
>
From: Kishon Vijay Abraham I
Date: Wed, 3 Apr 2013 12:05:30 +0530
> This patch series is about drivers/phy which will be used for now by
> usb, sata and maybe some video PHY's. Network itself has a
> comprehensive PHY in drivers/net/phy which we'd like to merge it with
> drivers/phy so that we ha
On Wed, Apr 3, 2013 at 2:27 PM, Thomas Petazzoni
wrote:
> Bjorn, Rob, Grant, Russell,
>
> Through this e-mail, I'd like to send you a kind reminder about this
> patch series. The latest version has been sent a week ago, and there
> has been only minor changes requested since v4 sent early March,
Hi,
On Wed, Apr 03, 2013 at 02:55:47PM +, Arnd Bergmann wrote:
> On Wednesday 03 April 2013, Felipe Balbi wrote:
> > const ? Maybe provide a:
> >
> > #define DEFINE_PHY_OPS(name)\
> > const struct phy_ops #name_phy_ops = {
> >
> > macro ? This will force people to add the const keyword :
Hi,
On Wed, Apr 03, 2013 at 08:02:52PM +0530, Kishon Vijay Abraham I wrote:
> + ret = -EINVAL;
> + goto err0;
> + }
> +
> + if (!phy_class)
> + phy_core_init();
> >>>
> >>>why don't you setup the class on module_init ? Then this would be a
> >>>terri
The UART driver enables the console uart clock, so we don't need to do that
anymore in this file.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra114.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/
Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: Peter De Schrijver
---
arch/arm/boot/dts/tegra114-dalmore.dts |1 -
arch/arm/b
Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: Peter De Schrijver
---
arch/arm/boot/dts/tegra114-dalmore.dts |1 -
arch/arm/b
On Wednesday 03 April 2013, Felipe Balbi wrote:
> const ? Maybe provide a:
>
> #define DEFINE_PHY_OPS(name)\
> const struct phy_ops #name_phy_ops = {
>
> macro ? This will force people to add the const keyword :-)
Forcing people to use const structures is good, but I think it would be
better
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk.c |1 +
drivers/clk/tegra/clk.h |6 ++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 70b7a47..923ca7e 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-periph-gate.c |9 +
drivers/clk/tegra/clk.h |2 ++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/clk-periph-gate.c
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver
---
.../bindings/clock/nvidia,tegra114-car.txt | 317
1 files changed, 317 insertions(+), 0 deletions(-)
create mode 100644
Docum
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-periph.c | 11 ++-
drivers/clk/tegra/clk-tegra20.c |2 +-
drivers/clk/te
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-pll.c | 839 +++
drivers/clk/tegra/clk.h | 50 +++-
2 files changed, 888 ins
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-pll.c |6 +++---
drivers/clk/tegra/clk-tegra20.c | 20 ++--
drivers
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-pll.c | 38 --
drivers/clk/tegra/clk-tegra20.c |7 +++
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |2 ++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/clk-
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-pll.c | 12
drivers/clk/tegra/clk.h |2 ++
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/dri
In preparation for moving the PCIe driver into the drivers/pci/host
directory, this header, which contains prototypes that are required by
the PCIe driver, needs to be moved to a globally visible location.
Signed-off-by: Thierry Reding
---
Changes in v2:
- keep tegra_pmc_init() prototype in arch/
The new struct msi_chip is used to associated an MSI controller with a
PCI bus. It is automatically handed down from the root to its children
during bus enumeration.
This patch provides default (weak) implementations for the architecture-
specific MSI functions (arch_setup_msi_irq(), arch_teardown
Enable the first PCIe root port which is connected to an FPGA on the
Tamonten Evaluation Carrier and add device nodes for each of the PCI
endpoints available in the standard configuration.
Signed-off-by: Thierry Reding
---
Changes in v2:
- remove duplicate nodes and properties defined in tegra20-
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding
---
drivers/of/of_pci.c| 25 +
include/linux/of_pci.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/of/of_pci
The PMC code already accesses to PMC registers so it makes sense to
move this function there as well. While at it, rename the function to
tegra_pmc_pcie_xclk_clamp() for consistency.
Signed-off-by: Thierry Reding
Acked-by: Stephen Warren
---
arch/arm/mach-tegra/pcie.c | 30 -
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry Reding
---
Changes in v2:
- rename devfn and err variables
Add properties common to all Tamonten-derived boards to the Tamonten
DTSI and add the fixed 1.05 V regulator.
Signed-off-by: Thierry Reding
---
Changes in v2:
- add properties common to all Tamonten boards
- add fixed 1.05 V regulator
arch/arm/boot/dts/tegra20-tamonten.dtsi | 17 +++
With the device tree support in place, probe the PCIe controller from
the device tree and remove the corresponding workaround in the board
file.
Signed-off-by: Thierry Reding
---
Changes in v2:
- add missing dummy regulator nodes by Stephen Warren
- rename port 0 DT node and disable unused port 1
From: Andrew Murray
This patch factors out common implementation patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This will make it easier to w
With the device tree support in place, probe the PCIe controller from
the device tree and remove the corresponding workaround in the board
file.
Signed-off-by: Thierry Reding
---
arch/arm/boot/dts/tegra20-harmony.dts | 20
1 file changed, 16 insertions(+), 4 deletions(-)
di
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* M
Enable PCI and MSI support as well as the new Tegra PCIe controller
driver.
Signed-off-by: Thierry Reding
---
arch/arm/configs/tegra_defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 2b42a2c.
This patch series contains an almost complete rewrite of the Tegra PCIe
driver. The code is moved to the drivers/pci/host directory and turned
into a proper platform driver, adding MSI and DT support while at it.
Other PCI host controller drivers can be added to that directory in an
attempt to make
tegra_boot_secondary() relies on some of the car ops. This means having an
uninitialized tegra_cpu_car_ops will lead to an early boot panic.
Providing a dummy struct avoids this and makes adding Tegra114 clock support
in a bisectable way a lot easier.
Signed-off-by: Peter De Schrijver
---
driver
This is the nineth version of the Tegra114 clockframework. It is based on the
next-20130320-fixed branch of
git://nv-tegra.nvidia.com/user/swarren/linux-2.6.git,
http://patchwork.ozlabs.org/patch/229972/ and
http://patchwork.ozlabs.org/patch/229978/ and
http://patchwork.ozlabs.org/patch/233415/
It
Hi,
On Wednesday 03 April 2013 07:57 PM, Felipe Balbi wrote:
hi,
On Wed, Apr 03, 2013 at 07:48:42PM +0530, Kishon Vijay Abraham I wrote:
+struct phy *of_phy_xlate(struct phy *phy, struct of_phandle_args *args)
+{
+ return phy;
+}
+EXPORT_SYMBOL_GPL(of_phy_xlate);
so you get a PHY and j
hi,
On Wed, Apr 03, 2013 at 07:48:42PM +0530, Kishon Vijay Abraham I wrote:
> >>+struct phy *of_phy_xlate(struct phy *phy, struct of_phandle_args *args)
> >>+{
> >>+ return phy;
> >>+}
> >>+EXPORT_SYMBOL_GPL(of_phy_xlate);
> >
> >so you get a PHY and just return it ? What gives ?? (maybe I skipp
On Mon, Mar 25, 2013 at 12:15:47PM +0100, Prashant Gaikwad wrote:
> On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:
> > The device tree binding models Tegra114 CAR (Clock And Reset) as a single
> > monolithic clock provider.
> >
> > Signed-off-by: Peter De Schrijver
> > ---
>
>
>
>
Hi,
On Wednesday 03 April 2013 07:12 PM, Felipe Balbi wrote:
On Wed, Apr 03, 2013 at 06:23:49PM +0530, Kishon Vijay Abraham I wrote:
The PHY framework provides a set of APIs for the PHY drivers to
create/destroy a PHY and APIs for the PHY users to obtain a reference to the
PHY with or without u
Enable m25p64 SPI flash support on da850-EVM. Also
add partition information of SPI flash.
Signed-off-by: Manjunathappa, Prakash
---
Since v2:
Fixed partition sizes.
Since v1:
Look for m25p64 instead of m25p80.
Corrected the filesystem partition information.
arch/arm/boot/dts/da850-evm.dts |
Populate OF_DEV_AUXDATA with desired device name expected by spi-davinci
driver. Without this clk_get of spi-davinci DT driver fails.
Signed-off-by: Manjunathappa, Prakash
---
arch/arm/mach-davinci/da8xx-dt.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-
Patch adds SPI1 DT node along with pinmux data.
Signed-off-by: Manjunathappa, Prakash
---
Since v4:
Separate out chip_select pinmuxing so as to allow boards choose
what to configure. Dropped unused CS1 and ENA pinmuxing.
arch/arm/boot/dts/da850.dtsi | 22 ++
1 files change
From: Murali Karicheri
Add binding documentation for spi-davinci module.
[prakash...@ti.com: Follow DT naming convention for compatible property]
Signed-off-by: Murali Karicheri
Reviewed-by: Grant Likely
Reviewed-by: Sekhar Nori
Signed-off-by: Manjunathappa, Prakash
---
Since v3:
Changed the
Testing information:
da850-evm comes with partitions specified in DT blob.
Able to mount/umount and create/delete files on filesystem partition.
Applies on top of linux_davinci/master tree:
git://gitorious.org/linux-davinci/linux-davinci.git
Since v4:
Separate out chip_select pinmuxing so as to a
Follow DT naming convention for compatible property of the blob.
Use first chip name that introduced the specific version of the
device.
Signed-off-by: Manjunathappa, Prakash
---
drivers/spi/spi-davinci.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi
On Wed, Apr 03, 2013 at 06:23:50PM +0530, Kishon Vijay Abraham I wrote:
> Used the generic PHY framework API to create the PHY. omap_usb2_suspend
> is split into omap_usb_suspend and omap_usb_resume in order to align
> with the new framework.
>
> However using the old USB PHY library cannot be com
On Wed, Apr 03, 2013 at 06:23:49PM +0530, Kishon Vijay Abraham I wrote:
> The PHY framework provides a set of APIs for the PHY drivers to
> create/destroy a PHY and APIs for the PHY users to obtain a reference to the
> PHY with or without using phandle. To obtain a reference to the PHY without
> us
From: Wei Yongjun
Fix to return a negative error code from the error handling
case instead of 0, as returned elsewhere in this function.
Signed-off-by: Wei Yongjun
---
drivers/spi/spi-mxs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index
In order for controllers to get PHY in case of non dt boot, the phy
binding information should be added in the platform specific
initialization code using phy_bind.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/usb-musb.c |7 ++-
1 file changed, 6 insertions(+), 1 deletio
Used the generic PHY framework API to create the PHY. twl4030_usb_suspend
and twl4030_usb_resume is added to phy_ops in order to align
with the new framework.
However using the old USB PHY library cannot be completely removed
because OTG is intertwined with PHY and moving to the new
framework comp
Use the generic PHY framework API to get the PHY. The usb_phy_set_suspend
and usb_phy_set_resume is replaced with phy_suspend and phy_resume to
align with the new PHY framework.
musb->xceiv can't be removed as of now because musb core uses xceiv.state and
xceiv.otg. Once there is a separate state
Added a generic PHY framework that provides a set of APIs for the PHY drivers
to create/destroy a PHY and APIs for the PHY users to obtain a reference to
the PHY with or without using phandle. To obtain a reference to the PHY
without using phandle, the platform specfic intialization code (say from
The PHY framework provides a set of APIs for the PHY drivers to
create/destroy a PHY and APIs for the PHY users to obtain a reference to the
PHY with or without using phandle. To obtain a reference to the PHY without
using phandle, the platform specfic intialization code (say from board file)
shoul
Updated the usb_otg_hs dt data to include the *phy* and *phy-names*
binding in order for the driver to use the new generic PHY framework.
Also updated the Documentation to include the binding information.
The PHY binding information can be found at
Documentation/devicetree/bindings/phy/phy-bindings
Used the generic PHY framework API to create the PHY. omap_usb2_suspend
is split into omap_usb_suspend and omap_usb_resume in order to align
with the new framework.
However using the old USB PHY library cannot be completely removed
because OTG is intertwined with PHY and moving to the new framewor
Hi Arun,
On 03/13/2013 05:09 AM, Arun Kumar K wrote:
> Hi Sylwester,
>
>>>
>>> /* Interrupt mask */
>>> #define S5PCSIS_INTMSK 0x10
>>> -#define S5PCSIS_INTMSK_EN_ALL0xf000103f
>>> +#define S5PCSIS_INTMSK_EN_ALL0xfc00103f
>>
>> Do you know w
Bjorn, Rob, Grant, Russell,
Through this e-mail, I'd like to send you a kind reminder about this
patch series. The latest version has been sent a week ago, and there
has been only minor changes requested since v4 sent early March, i.e a
month ago. Therefore, I would hope for this series to enter 3
Hi,
On Wed, Mar 20, 2013 at 16:16:57, Manjunathappa, Prakash wrote:
> Patch adds SPI1 DT node along with pinmux data.
>
> Signed-off-by: Manjunathappa, Prakash
> ---
> arch/arm/boot/dts/da850.dtsi | 18 ++
> 1 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/a
Hi Matt,
On 3/6/2013 9:45 PM, Matt Porter wrote:
> This series adds DMA Engine support for AM33xx, which uses
> an EDMA DMAC. The EDMA DMAC has been previously supported by only
> a private API implementation (much like the situation with OMAP
> DMA) found on the DaVinci family of SoCs.
> Matt P
On Wed, Apr 3, 2013 at 1:46 AM, Mike Turquette wrote:
> Quoting Sebastian Hesselbarth (2013-03-23 07:46:50)
>> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
>> new file mode 100644
>> index 000..9d0c210
>> --- /dev/null
>> +++ b/drivers/clk/clk-si5351.c
>> @@ -0,0 +1,1411 @@
Dear Jason Cooper,
On Wed, 3 Apr 2013 06:57:57 -0400, Jason Cooper wrote:
> Thanks for pointing this out. I'll put it in mvebu/drivers as you
> suggested. I'll need to rebase mvebu/soc on it. But I haven't done the
> PR yet, so not a big deal.
Ok, thanks. I'll finalize the cleanup of the kirk
Thomas,
On Wed, Apr 03, 2013 at 12:52:47PM +0200, Thomas Petazzoni wrote:
> Jason (Cooper),
>
> Do you mind taking this patch in your mvebu/drivers branch, next to the
> patch adding the mvebu-mbus driver? Or do you want a new mvebu-mbus
> driver patch that contains this fix and would replace the
Jason (Cooper),
Do you mind taking this patch in your mvebu/drivers branch, next to the
patch adding the mvebu-mbus driver? Or do you want a new mvebu-mbus
driver patch that contains this fix and would replace the one you have
already merged in mvebu/drivers?
Thanks!
Thomas
On Wed, 27 Mar 2013
Le 03/29/13 19:14, Florian Fainelli a écrit :
This patch modifies kirkwood.dtsi to specify the various gigabit
interfaces nodes available on kirkwood devices. They are disabled by
default and should be enabled on a per-board basis. egiga0 and egiga1
aliases are defined for convenience. The mdio n
Hi
This 2 patches add DT irqpin support on marzen-reference. Only
compile-tested due to the lack of hardware. The patches can go
independently via their respective trees. irqpin on marzen will not work
if patch 2 is applied before patch 1, but as long as there are no devices,
using irqpin inte
Add an irqpin interrupt controller DT node on marzen-reference.
Signed-off-by: Guennadi Liakhovetski
---
arch/arm/boot/dts/r8a7779.dtsi | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index
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