Okay now I have finished my criticism, I will make some productive
suggestions :)
How about we implement a system as follows; modify the clock framework
and bindings such that we not only describe all the parents possible
for a clock, we also enter into the device tree the current parent? I
actual
On Thu, Apr 4, 2013 at 6:08 PM, Fabio Estevam wrote:
>
> This could be useful for removing the imx6q_sabrelite_cko1_setup()
> function from arch/arm/mach-imx/mach-imx6q.c.
>
> I would like to add audio support for another board and would like to
> avoid to do the same as imx6q_sabrelite_cko1_setup
On Thursday 04 of April 2013 18:36:57 Tomasz Figa wrote:
> This series is an attempt to make the samsung-time clocksource driver
> ready for multiplatform kernels. It moves the driver to
> drivers/clocksource, cleans it up from uses of static platform-specific
> definitions, simplifies timer interr
On Friday 05 of April 2013 21:54:21 Arnd Bergmann wrote:
> On Friday 05 April 2013, Tomasz Figa wrote:
> > > I don't think anyone ever suggested using a private API though.
> >
> > I must have gotten the last paragraph of
> > http://article.gmane.org/gmane.linux.kernel.samsung-soc/16638
> > wrong
On 04/05/2013 10:50 PM, Arnd Bergmann wrote:
> On Friday 05 April 2013, Gregory CLEMENT wrote:
>> From: Lior Amsalem
>>
>> In order to be able to support he LPAE, the internal registers virtual
>> base must be aligned to 2MB.
>>
>> Signed-off-by: Lior Amsalem
>> Signed-off-by: Gregory CLEMENT
>
On 04/05/2013 10:46 PM, Arnd Bergmann wrote:
> On Friday 05 April 2013, Gregory CLEMENT wrote:
>> The Armada XP SoCs have LPAE support. This is the second version patch
>> set whixh allow to run kernel on this SoCs with LPAE support.
>>
>> The biggest changes are the conversion of the device tree f
On 04/05/2013 10:41 PM, Arnd Bergmann wrote:
> On Friday 05 April 2013, Gregory CLEMENT wrote:
>> When LPAE is activated on Armada XP, all registers and IOs are still
>> 32bit, the 40bit extension is on the CPU to DRAM path (windows) only.
>> That means that all the DMA transfer are restricted to t
On Friday 05 April 2013, Gregory CLEMENT wrote:
> From: Lior Amsalem
>
> In order to be able to support he LPAE, the internal registers virtual
> base must be aligned to 2MB.
>
> Signed-off-by: Lior Amsalem
> Signed-off-by: Gregory CLEMENT
This is a surprising limitation. Can you extend the a
On 04/05/2013 10:43 PM, Arnd Bergmann wrote:
> On Friday 05 April 2013, Gregory CLEMENT wrote:
>> Signed-off-by: Gregory CLEMENT
>
> The patch looks good but the description is a bit short.
>
It cannot be more brief! :)
I explained the purpose of this patch in the cover letter and forgot to
ad
On Friday 05 April 2013, Gregory CLEMENT wrote:
> The Armada XP SoCs have LPAE support. This is the second version patch
> set whixh allow to run kernel on this SoCs with LPAE support.
>
> The biggest changes are the conversion of the device tree file to 64
> bits in order to be able to use more t
On Friday 05 April 2013, Gregory CLEMENT wrote:
> From: Thomas Petazzoni
>
> Signed-off-by: Thomas Petazzoni
This should have a description, even though it's completely trivial.
I would also recommend moving this patch first, as the general rule
is to do cleanups first.
Arnd
__
On Friday 05 April 2013, Gregory CLEMENT wrote:
> Signed-off-by: Gregory CLEMENT
The patch looks good but the description is a bit short.
Arnd
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On Friday 05 April 2013, Gregory CLEMENT wrote:
> When LPAE is activated on Armada XP, all registers and IOs are still
> 32bit, the 40bit extension is on the CPU to DRAM path (windows) only.
> That means that all the DMA transfer are restricted to the low 32 bits
> address space. This is limitation
From: Thomas Petazzoni
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 28
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 28
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 54 +++---
3 files changed, 55 inse
In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.
Armada XP and Armada 370 share a dtsi file which have also be
converted to 64 bits. This lead to convert all the device tree files
to 64 bits even the one used for Armada 370 (which do
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-db.dts | 108 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 78
arch/arm/boot/dts/armada-370-rd.dts |2 +
arch/arm/boot/dts/armada-370-xp.dtsi | 228 +++--
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-370-db.dts
From: Thomas Petazzoni
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-370-xp.dtsi | 26 +-
arch/arm/boot/dts/armada-370.dtsi| 23 ---
arch/arm/boot/dts/armada-xp.dtsi | 32
3 files changed,
From: Lior Amsalem
In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2
Signed-off-by: Gregory CLEMENT
Signed-off-by: Lior Amsalem
---
arch/arm/boot/dts/skeleton64.dtsi | 13 +
1 file changed, 13 insertions(+)
create mode 100644 arch/arm/boo
From: Lior Amsalem
pj4b cpus are LPAE capable so enable them on LPAE compilations
Signed-off-by: Lior Amsalem
Tested-by: Franklin
Signed-off-by: Gregory CLEMENT
---
arch/arm/mm/proc-v7.S |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm
From: Lior Amsalem
In order to be able to support he LPAE, the internal registers virtual
base must be aligned to 2MB.
Signed-off-by: Lior Amsalem
Signed-off-by: Gregory CLEMENT
---
arch/arm/include/debug/mvebu.S |2 +-
arch/arm/mach-mvebu/armada-370-xp.h |2 +-
2 files changed,
Hello,
The Armada XP SoCs have LPAE support. This is the second version patch
set whixh allow to run kernel on this SoCs with LPAE support.
The biggest changes are the conversion of the device tree file to 64
bits in order to be able to use more than 4GB of memory (without this
the LPAE is pointl
When LPAE is activated on Armada XP, all registers and IOs are still
32bit, the 40bit extension is on the CPU to DRAM path (windows) only.
That means that all the DMA transfer are restricted to the low 32 bits
address space. This is limitation is achieved by selecting ZONE_DMA.
Signed-off-by: Greg
On 04/05/2013 01:37 PM, Simon Glass wrote:
> HI Wolfram,
>
> On Wed, Apr 3, 2013 at 12:19 PM, Wolfram Sang wrote:
>> Doug,
>>
>>> Separately from a discussion of the technical merits, I'd say that
>>> this patch is needed because the Embedded Controller (EC) on the ARM
>>> Chromebook shipped expe
On Friday 05 April 2013, Tomasz Figa wrote:
> > I don't think anyone ever suggested using a private API though.
>
> I must have gotten the last paragraph of
> http://article.gmane.org/gmane.linux.kernel.samsung-soc/16638
> wrong then. For me it seemed like the timer driver would expose a private A
HI Wolfram,
On Wed, Apr 3, 2013 at 12:19 PM, Wolfram Sang wrote:
> Doug,
>
>> Separately from a discussion of the technical merits, I'd say that
>> this patch is needed because the Embedded Controller (EC) on the ARM
>> Chromebook shipped expecting to communicate with this scheme. While
>
> Uhrm
On 04/05/2013 01:46 PM, Stephen Warren wrote:
> Rob, it might be worth keeping this in a separate branch in linux-next
> so you can pull it out if it causes any issues. I've been using these
> patches for quite a while now, but there's always opportunity for
> surprises on architectures I don't use
Rob, it might be worth keeping this in a separate branch in linux-next
so you can pull it out if it causes any issues. I've been using these
patches for quite a while now, but there's always opportunity for
surprises on architectures I don't use. I did just fix a bug when
building with O= a few day
On 04/05/2013 08:04 PM, Jason Gunthorpe wrote:
On Fri, Apr 05, 2013 at 03:58:03PM +0200, Sebastian Hesselbarth wrote:
I don't think that the ethernet controller should probe the PHY's on mdio-bus
at all. At least not for DT enabled platforms. I had a look at DT and non-DT
mdio-bus sources, and r
On 04/05/2013 11:57 AM, Will Deacon wrote:
> Hi Rob,
>
> On Fri, Apr 05, 2013 at 05:43:06PM +0100, Rob Herring wrote:
[...]
>>> +- compatible: Should be one of "arm,smmu-v1" or "arm,smmu-v2"
>>> + depending on the version of the architecture
>>> + implemente
On Fri, Apr 05, 2013 at 03:58:03PM +0200, Sebastian Hesselbarth wrote:
> I don't think that the ethernet controller should probe the PHY's on mdio-bus
> at all. At least not for DT enabled platforms. I had a look at DT and non-DT
> mdio-bus sources, and realized that there is a bus scan for non-DT
On Friday 05 of April 2013 19:05:24 Arnd Bergmann wrote:
> On Friday 05 April 2013, Tomasz Figa wrote:
> > On Friday 05 of April 2013 18:39:58 Samuel Ortiz wrote:
> > > Hi Tomasz,
> > >
> > > On Thu, Apr 04, 2013 at 06:37:01PM +0200, Tomasz Figa wrote:
> > > > This patch adds master driver for PWM
On Thu, Mar 14, 2013 at 3:14 PM, Christian Daudt wrote:
> - Adds devicetree binding and documentation for the smc handler
>
> Updates from V1:
> - Created this separate patch for the DT portion
> - Added SoC compatible to smc binding
> ...
any willing reviewers ?
Thanks,
csd
_
On Friday 05 April 2013, Tomasz Figa wrote:
> On Friday 05 of April 2013 18:39:58 Samuel Ortiz wrote:
> > Hi Tomasz,
> >
> > On Thu, Apr 04, 2013 at 06:37:01PM +0200, Tomasz Figa wrote:
> > > This patch adds master driver for PWM/timer block available on many
> > > Samsung SoCs providing clocksour
Hi Rob,
On Fri, Apr 05, 2013 at 05:43:06PM +0100, Rob Herring wrote:
> On 04/04/2013 11:50 AM, Will Deacon wrote:
> > This patch adds a description of the device tree binding for the ARM
> > System MMU architecture.
> >
> > Cc: Rob Herring
> > Cc: Andreas Herrmann
> > Signed-off-by: Will Deacon
Hi Samuel,
On Friday 05 of April 2013 18:39:58 Samuel Ortiz wrote:
> Hi Tomasz,
>
> On Thu, Apr 04, 2013 at 06:37:01PM +0200, Tomasz Figa wrote:
> > This patch adds master driver for PWM/timer block available on many
> > Samsung SoCs providing clocksource and PWM output capabilities.
> >
> > Sig
On 04/04/2013 11:50 AM, Will Deacon wrote:
> This patch adds a description of the device tree binding for the ARM
> System MMU architecture.
>
> Cc: Rob Herring
> Cc: Andreas Herrmann
> Signed-off-by: Will Deacon
> ---
>
> Hello,
>
> The driver for this is still a WIP. Both Andreas and myself
Hi Tomasz,
On Thu, Apr 04, 2013 at 06:37:01PM +0200, Tomasz Figa wrote:
> This patch adds master driver for PWM/timer block available on many
> Samsung SoCs providing clocksource and PWM output capabilities.
>
> Signed-off-by: Tomasz Figa
> Signed-off-by: Kyungmin Park
> ---
> .../devicetree/b
Hi Ian,
On Fri, Mar 22, 2013 at 02:55:13PM +, Ian Lartey wrote:
> @@ -278,20 +329,20 @@ static void palmas_dt_to_pdata(struct i2c_client *i2c,
> int ret;
> u32 prop;
>
> - ret = of_property_read_u32(node, "ti,mux_pad1", &prop);
> + ret = of_property_read_u32(node, "ti,mux
Hi Ian,
On Fri, Mar 22, 2013 at 02:55:10PM +, Ian Lartey wrote:
> This patchset adds to the support for the Palmas series of PMIC chips.
>
> Some of the patches have previously been submitted individually.
> The DT bindings doc has been added first due to comments that it was missing.
>
> Pa
Hi Linus,
On Fri, Mar 01, 2013 at 01:07:26PM +0100, Linus Walleij wrote:
> From: Gabriel Fernandez
>
> This patch augments the STMP driver to read the device id
> from the stmpe-i2c dt alias if present.
>
> Cc: devicetree-discuss@lists.ozlabs.org
> Signed-off-by: Gabriel Fernandez
> Signed-off
On 04/04/2013 08:01 PM, Stephen Warren wrote:
> On 04/04/2013 05:17 PM, Rob Herring wrote:
>> On 04/03/2013 06:34 PM, Stephen Warren wrote:
>>> From: Stephen Warren
>>>
>>> The recent dtc+cpp support allows header files and C pre-processor
>>> defines/macros to be used when compiling device tree f
Hi Linus,
On Fri, Mar 01, 2013 at 01:07:16PM +0100, Linus Walleij wrote:
> From: Gabriel Fernandez
>
> If there is no interrupt property into stmpe node
> then activate the no-irq mode by setting the irq
> value to -1.
>
> Cc: devicetree-discuss@lists.ozlabs.org
> Signed-off-by: Gabriel Fernand
* Roger Quadros [130405 03:44]:
> On 04/04/2013 07:41 PM, Tony Lindgren wrote:
> > * Roger Quadros [130404 00:39]:
> >> On 04/04/2013 02:42 AM, Tony Lindgren wrote:
> > For v3.10, let's just make sure that USB works with DT as then
> > after v3.10 we can make omap4 DT only and get rid of estimate
Mike,
Could we have your opinion on the below patch, and possibly an Acked-by
to carry it through the arm-soc tree?
Thanks,
Thomas
On Wed, 27 Mar 2013 15:40:24 +0100, Thomas Petazzoni wrote:
> The current revision of the datasheet only mentions the gatable clocks
> for the PCIe 0.0, 0.1, 0.2 an
Hello Sebastian,
Le 04/05/13 15:58, Sebastian Hesselbarth a écrit :
On Fri, Apr 5, 2013 at 11:56 AM, Florian Fainelli wrote:
[snip]
Florian,
took me a while to try you patches out on Dove but now I fixed all
issues. I will
comment on all related patches but first I want to comment here.
On
Mike,
Could we have your opinion on this patch, and possibly a Acked-by to
pass it through arm-soc?
Thanks!
Thomas
On Wed, 27 Mar 2013 15:40:23 +0100, Thomas Petazzoni wrote:
> The Armada 370 has two gatable clocks for each PCIe interface, and we
> want both of them to be enabled. We therefore
On Fri, Apr 5, 2013 at 11:56 AM, Florian Fainelli wrote:
> [snip]
Florian,
took me a while to try you patches out on Dove but now I fixed all
issues. I will
comment on all related patches but first I want to comment here.
One general note for Dove related patches: You didn't remove the registra
On Fri, Apr 05, 2013 at 09:45:36PM +0800, Wei Yongjun wrote:
> From: Wei Yongjun
>
> Neither tegra20_spi_cdata nor tegra30_spi_cdata are used outside this
> file so they can, and should, be static.
>
> Signed-off-by: Wei Yongjun
> ---
> drivers/spi/spi-tegra20-slink.c | 4 ++--
> 1 file change
On 04/05/2013 08:23 AM, Padmavathi Venna wrote:
> Audio subsystem is introduced in exynos platforms. This has seperate
> clock controller which can control i2s0 and pcm0 clocks. This patch
> registers the audio subsystem clocks with the common clock framework.
>
> Signed-off-by: Padmavathi Venna
From: Wei Yongjun
Neither tegra20_spi_cdata nor tegra30_spi_cdata are used outside this
file so they can, and should, be static.
Signed-off-by: Wei Yongjun
---
drivers/spi/spi-tegra20-slink.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-tegra20-slink.
On Wednesday 06 March 2013 07:42 PM, Matt Porter wrote:
Changes since v2:
- dropped skip platform_get_resource_byname() patch
Changes since v1:
- rebase to 3.9-rc1, previous dependencies upstream
This series adds DT DMA Engine Client support to the omap_hsmmc.
It leverages the ge
Hi Padmavathi,
On 04/05/2013 08:40 AM, Padmavathi Venna wrote:
> Samsung Exynos SoC has a separate subsystem for audio. This subsystem
> has a internal clock controller which controls i2s0 and pcm0 clocks.
> This patch series adds the Samsung Exynos SoC audio subsytem clock code
> to the common cl
On 04/05/2013 01:35 AM, Santosh Shilimkar wrote:
> On Friday 05 April 2013 01:46 AM, Jon Hunter wrote:
>> Main change is ensuring that the state of a gpio bank is restored when
>> booting with device-tree. The rest of the patches are clean-ups and one
>> optimisation.
>>
>> The patch modifying the
On 04/04/2013 07:41 PM, Tony Lindgren wrote:
> * Roger Quadros [130404 00:39]:
>> On 04/04/2013 02:42 AM, Tony Lindgren wrote:
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -27,6 +27,7 @@
#include
#include
#include
>>
Hi Heiko,
On Friday 05 of April 2013 01:15:02 Heiko Stübner wrote:
> Am Donnerstag, 4. April 2013, 18:36:57 schrieb Tomasz Figa:
> > This series is an attempt to make the samsung-time clocksource driver
> > ready
> > for multiplatform kernels. It moves the driver to drivers/clocksource,
> > cleans
From: Christian Hemp
Based on Sascha Hauer's patch i.MX27 clock: Do not disable lcd clocks during
startup.
This patch gives a interface to chance the alphavalue of the framebuffer.
Signed-off-by: Christian Hemp
rebased to 3.7
Signed-off-by: Markus Pargmann
---
drivers/video/imxfb.c
Add devicetree support for imx framebuffer driver. It uses the generic
display bindings and helper functions.
Signed-off-by: Markus Pargmann
Cc: Fabio Estevam
Cc: Mark Rutland
---
.../devicetree/bindings/video/fsl,imx-fb.txt | 49 ++
drivers/video/imxfb.c
Hi,
This series adds DT support for imxfb. Changes in v3 are
described in the notes of patch 2.
Regards,
Markus
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On Thu, Apr 04, 2013 at 06:17:20PM +0200, Tomasz Figa wrote:
> + if (of_property_read_u32(np, "max8952,ramp-speed", &pd->ramp_speed))
> + dev_warn(dev, "max8952,ramp-speed property not specified,
> defaulting to 32mV/us\n");
Applied both, though the above warning seems a bit hars
Add DT binding documentation for the FIMD IP block found in Samsung SoCs.
Signed-off-by: Vikas Sajjan
Reviewed-by: Sylwester Nawrocki
---
.../devicetree/bindings/video/samsung-fimd.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree
This patch adds FIMD related nodes for the Origen Quad board.
Signed-off-by: Vikas Sajjan
Reviewed-by: Sylwester Nawrocki
---
arch/arm/boot/dts/exynos4412-origen.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/
This patch adds a common FIMD device node for all Exynos4 SoCs.
Signed-off-by: Vikas Sajjan
Reviewed-by: Sylwester Nawrocki
---
arch/arm/boot/dts/exynos4.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
inde
This patch series adds support for DRM FIMD DT for Exynos4 DT Machines,
specifically for Exynos4412 SoC.
changes since v10:
- addressed comments from Sylwester Nawrocki
changes since v9:
- dropped the patch "ARM: dts: Add lcd pinctrl node entries for
EXYNOS4412 SoC"
as
Hello Simon,
First of all, thanks for getting these patches a try!
Le 04/04/13 23:29, Simon Baatz a écrit :
Hi Florian
[snip]
if (!mv643xx_eth_version_printed++)
pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
This is not related to your change, but
Most Renesas irqpin controllers have 4-bit sense fields, however, some
have different widths. This patch adds a DT binding to optionally
specify such non-standard values.
Signed-off-by: Guennadi Liakhovetski
---
v2: is no longer based on an earlier "ARM: shmobile: irqpin: fix handling
of spurio
Le 04/04/13 23:35, Simon Baatz a écrit :
Hi Florian,
On Thu, Apr 04, 2013 at 12:27:13PM +0200, Florian Fainelli wrote:
This patch modifies kirkwood.dtsi to specify the various gigabit
interfaces nodes available on kirkwood devices. They are disabled by
default and should be enabled on a per-boa
On Thu, Apr 04, 2013 at 03:16:14PM -0500, Jon Hunter wrote:
> The OMAP GPIO interrupt service routine is checking each bit in the
> GPIO interrupt status register to see which bits are set. It is not
> efficient to check every bit especially if only a few bits are set.
> Therefore, instead of check
On 04/04/2013 10:45 PM, Stephen Warren wrote:
> On 03/26/2013 09:58 AM, Sylwester Nawrocki wrote:
>> From: Guennadi Liakhovetski
>>
>> This patch adds a document describing common OF bindings for video
>> capture, output and video processing devices. It is curently mainly
>> focused on video captu
On 04/05/2013 11:48 AM, Nishanth Menon wrote:
> On 11:47-20130405, Roger Quadros wrote:
>> On 04/02/2013 11:23 AM, Roger Quadros wrote:
>>> + Paul
>>>
>>> On 03/26/2013 12:23 PM, Roger Quadros wrote:
>>>> Register a device tree clock provider for th
On 11:47-20130405, Roger Quadros wrote:
> On 04/02/2013 11:23 AM, Roger Quadros wrote:
> > + Paul
> >
> > On 03/26/2013 12:23 PM, Roger Quadros wrote:
> >> Register a device tree clock provider for the clocks
> >> on the OMAP4 SoC. Also provide the binding
On 04/02/2013 11:23 AM, Roger Quadros wrote:
> + Paul
>
> On 03/26/2013 12:23 PM, Roger Quadros wrote:
>> Register a device tree clock provider for the clocks
>> on the OMAP4 SoC. Also provide the binding information.
>>
>> For now we only provide AUXCLKs.
NOTE: this patch depends on
https://patc
On Friday 05 April 2013 01:52 PM, Benoit Cousson wrote:
> Santosh and Jon,
>
> On 04/05/2013 10:08 AM, Benoit Cousson wrote:
>> On 04/05/2013 08:26 AM, Santosh Shilimkar wrote:
>>> On Thursday 04 April 2013 11:36 PM, Jon Hunter wrote:
The L3 interrupt numbers are incorrect for OMAP4+ and are
Santosh and Jon,
On 04/05/2013 10:08 AM, Benoit Cousson wrote:
> On 04/05/2013 08:26 AM, Santosh Shilimkar wrote:
>> On Thursday 04 April 2013 11:36 PM, Jon Hunter wrote:
>>> The L3 interrupt numbers are incorrect for OMAP4+ and are conflicting
>>> with some of the timer interrupts causing the all
On 04/05/2013 08:26 AM, Santosh Shilimkar wrote:
> On Thursday 04 April 2013 11:36 PM, Jon Hunter wrote:
>> The L3 interrupt numbers are incorrect for OMAP4+ and are conflicting
>> with some of the timer interrupts causing the allocation of timer
>> interrupts to fail.
>>
>> The problem is caused b
On 04/04/2013 08:38 PM, Tony Lindgren wrote:
> * Jon Hunter [130319 10:42]:
>> Includes:
>> - A couple fixes for DMTIMER context loss handling.
>> - Populating DMTIMER errata when booting with device-tree.
>> - A new function for requesting a DMTIMER by device-tree node.
>>
>> Based upon v3.9-rc3.
On Fri, Apr 05, 2013 at 03:45:12PM +0800, Wei Yongjun wrote:
> From: Wei Yongjun
>
> symbol '' was not declared. It should be static.
This description doesn't make any sense. The patch looks good, though.
Maybe something like:
---snip---
Neither tegra20_spi_cdata nor tegra30_spi_cdata are used
For reference, here's the new binding document with all your comments
addressed (I think).
Thierry
NVIDIA Tegra PCIe controller
Required properties:
- compatible: "nvidia,tegra20-pcie"
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
regi
According to
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
the "#interrupt-cells" property of an "interrupt-controller" is used
to define the number of cells needed to specify a single interrupt.
A commonly used variant is two cell on which #interrupt-cells = <2>
and the f
From: Wei Yongjun
symbol '' was not declared. It should be static.
Signed-off-by: Wei Yongjun
---
drivers/spi/spi-tegra20-slink.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index 4e58b53..b224a82 100
On Thu, Apr 04, 2013 at 03:28:54PM -0600, Stephen Warren wrote:
[...]
> > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> > b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
>
> > +Required properties:
>
> > +- interrupts: the interrupt outputs of the c
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