Hi Laurent,
On Wed, May 15, 2013 at 6:54 PM, Laurent Pinchart
wrote:
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Wednesday 15 May 2013 18:22:29 Lad Prabhakar wrote:
>> From: Lad, Prabhakar
>>
>> This patch adds "field-active" and "sync-on-green" as part of
>> endpoint properties and also
Tuesday, May 14, 2013 11:17 PM, Vikas Sajjan wrote:
>
> Hi Vikas,
>
> On Tuesday 14 of May 2013 18:25:51 Vikas Sajjan wrote:
> > Adds GPIO parsing functionality for "LCD backlight" and "LCD enable"
> > GPIO pins of exynos dp controller.
> >
> > Signed-off-by: Vikas Sajjan
> > ---
> > drivers/
On 05/15/2013 06:13 PM, Tomasz Figa wrote:
> On Wednesday 15 of May 2013 16:55:37 Doug Anderson wrote:
>> Tomasz / Linus,
>>
>> On Wed, May 15, 2013 at 3:06 PM, Tomasz Figa
> wrote:
>>> Yes. I don't like the current way too much either, duplication being
>>> one of the reasons.
>>
>> Do you have
On Wednesday 15 of May 2013 17:03:44 Doug Anderson wrote:
> Stephen,
>
> On Wed, May 15, 2013 at 4:51 PM, Stephen Warren
wrote:
> > I don't really see much disadvantage here; the interrupt bindings
> > specify things related to interrupts and the pinctrl bindings specify
> > thing related to pin
On Wednesday 15 of May 2013 16:55:37 Doug Anderson wrote:
> Tomasz / Linus,
>
> On Wed, May 15, 2013 at 3:06 PM, Tomasz Figa
wrote:
> > Yes. I don't like the current way too much either, duplication being
> > one of the reasons.
>
> Do you have any other ideas? It sounds like Linus didn't like
On 05/10/2013 02:25 AM, Christian Ruppert wrote:
> On Wed, May 08, 2013 at 02:01:53PM -0600, Stephen Warren wrote:
>> On 05/08/2013 10:41 AM, Christian Ruppert wrote:
>> ...
>>> What do you think about the following modification to the pinctrl/GPIO
>>> frameworks instead (not yet a formal patch, mo
On 05/15/2013 12:29 PM, Linus Walleij wrote:
> On Wed, May 15, 2013 at 6:44 PM, Doug Anderson wrote:
...
>> Here's how I need to do things when I'm using "just an interrupt":
>>
>> pinctrl@1140 {
>> cyapa_irq: cyapa-irq {
>> samsung,pins = "gpx1-2";
>> samsung,pin-function =
On 05/10/13 08:02, James Hogan wrote:
> This adds a metag architecture specific clk-gate and clk-mux which
> extends the generic ones to use global lock2 to protect the register
> fields. It is common with metag to have an RTOS running on a different
> thread or core with access to different bits i
On Wednesday 15 of May 2013 15:01:23 Doug Anderson wrote:
> Tomasz,
>
> On Wed, May 15, 2013 at 2:41 PM, Tomasz Figa
wrote:
> > This will be hard, since the phandle in interrupt-parent is
> > represented by an IRQ domain in kernel code. One-interrupt IRQ
> > domains seem a bit awkward to me.
> >
On Wednesday 15 of May 2013 23:41:54 Tomasz Figa wrote:
> On Wednesday 15 of May 2013 14:31:20 Doug Anderson wrote:
> > Linus,
> >
> > Thank you for your comments. See below...
> >
> > Stephen: sorry for missing you earlier! :(
> >
> > On Wed, May 15, 2013 at 11:29 AM, Linus Walleij
> >
> >
Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> The Armada 370 has two gatable clocks for each PCIe interface, and we
> want both of them to be enabled. We therefore make one of the two
> clocks a child of the other, as we did for the sataX and sataXlnk
> clocks on Armada XP.
>
Ack for patches #
On Wednesday 15 of May 2013 14:31:20 Doug Anderson wrote:
> Linus,
>
> Thank you for your comments. See below...
>
> Stephen: sorry for missing you earlier! :(
>
> On Wed, May 15, 2013 at 11:29 AM, Linus Walleij
>
> wrote:
> > But please use the preprocessor to provide symbolic names for
> >
On Wednesday 15 of May 2013 14:19:18 Doug Anderson wrote:
> Tomasz,
>
> Thanks for your comments. I'm glad I'm not totally off-track. I'll
> respond to most things in reply to Linus' email, but a few here:
>
> On Wed, May 15, 2013 at 10:26 AM, Tomasz Figa
wrote:
> >> pinctrl@1140 {
> >>
On Tue, May 14, 2013 at 06:26:52PM +0200, Simon Baatz wrote:
> On Tue, May 14, 2013 at 08:37:47AM +0200, Guennadi Liakhovetski wrote:
> > On Mon, 13 May 2013, Simon Baatz wrote:
> >
> > > While adding DT support for the Sheevaplugs by Globalscale Technologies
> > > (Kirkwood), it turned out that t
On Wed, May 8, 2013 at 4:11 PM, Srinivas KANDAGATLA
wrote:
> From: Srinivas Kandagatla
>
> The STiH416 is advanced HD AVC processor with 3D graphics acceleration
> and 1.2-GHz ARM Cortex-A9 SMP CPU.
>
> Signed-off-by: Srinivas Kandagatla
> CC: Stephen Gallimore
> CC: Stuart Menefy
(...)
Thi
On Fri, May 3, 2013 at 11:09 AM, James Hogan wrote:
> Hi Linus,
> On 03/05/13 09:49, Linus Walleij wrote:
>> On Fri, Apr 26, 2013 at 11:22 AM, James Hogan wrote:
>>> So basically a bunch of global registers (e.g. pinctrl and gpio) are
>>> shared between all 3 cores (up to 4 OSes). The __global_lo
On Tue, May 14, 2013 at 2:22 PM, James Hogan wrote:
> I think that's the other way around, i.e. that's talking about mapping
> several pingroups to the same function. The next paragraph is closer to
> the problem:
>
> Documentation/pinctrl.txt
>> - PINS for a certain FUNCTION using a certain PIN
On Wed, May 15, 2013 at 6:44 PM, Doug Anderson wrote:
Pls include Stephen Warren on mailings regarding DT mappings,
he's very good at this stuff.
> I'm running into an issue when trying to specify pullups /
> pulldowns and drive strengths on lines that are just GPIOs or just
> interrupts. This
On Wed, May 15, 2013 at 10:26 AM, Tomasz Figa wrote:
>> I don't want to specify function/direction (code can handle that), but
>> do wish I could specify the pulls and strength. Perhaps:
>>
>> ptn3460-bridge@20 {
>> compatible = "nxp,ptn3460";
>> reg = <0x20>;
>> powerdown-gpio = <
Hi Doug,
There is no better way at the moment, but...
On Wednesday 15 of May 2013 09:44:22 Doug Anderson wrote:
> Linus,
>
> I'm currently working towards adapting exynos5250-snow (the ARM
> Chromebook) to work well in the new world of pinctrl. We've got a
> backport of exynos5250 pinctrl in ou
On 12:36 Wed 15 May , Eduardo Valentin wrote:
> On 15-05-2013 11:23, Benoit Cousson wrote:
> > Hi Eduardo,
> >
> > On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
> >> Include bandgap devices for OMAP4460 devices.
> >>
> >> Cc: "Benoît Cousson"
> >> Cc: Tony Lindgren
> >> Cc: Russell King
>
On 11:46-20130515, Dan Murphy wrote:
> The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
> are different.
>
> A1-A3 = gpio_wk7
> ES = gpio_110
>
> There is no change to LED D2
>
> Abstract away the pinmux and the LED definitions for the two board
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
---
arch/arm/boot/dts/aks-cdu.dts | 10 -
arch/arm/boot/dts/animeo_ip.dts | 16 +++---
arch/arm/boot/dts/at91-ariag25.dts |4 ++--
arch/arm/boot/dts/at91rm9200.dtsi
Hi Eduardo,
On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
> Include bandgap devices for OMAP4460 devices.
>
> Cc: "Benoît Cousson"
> Cc: Tony Lindgren
> Cc: Russell King
> Cc: linux-o...@vger.kernel.org
> Cc: devicetree-discuss@lists.ozlabs.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc
On Wed, May 15, 2013 at 4:03 PM, Jean-Christophe PLAGNIOL-VILLARD
wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
> Cc: Nicolas Ferre
Thanks, this makes the device trees much more readable.
Acked-by: Linus Walleij
Yours,
Linus Walleij
___
On Wed, May 15, 2013 at 03:51:43PM +0100, Nicolas Pitre wrote:
> On Wed, 15 May 2013, Lorenzo Pieralisi wrote:
>
> > On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
> > > On Tue, 14 May 2013, Javi Merino wrote:
> > >
> > > > On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pierali
On Wed, 15 May 2013, Lorenzo Pieralisi wrote:
> On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
> > On Tue, 14 May 2013, Javi Merino wrote:
> >
> > > On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> > >
> > > > +static inline void init_cpu_port(struct cpu_port
to prepare the switch to the macro.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
---
arch/arm/boot/dts/aks-cdu.dts |2 +-
arch/arm/boot/dts/animeo_ip.dts |2 +-
arch/arm/boot/dts/at91-ariag25.dts |2 +-
arch/arm/boot/dts/at91rm
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
---
arch/arm/boot/dts/at91rm9200.dtsi | 45 +++-
arch/arm/boot/dts/at91sam9260.dtsi | 49 --
arch/arm/boot/dts/at91sam9263.dtsi | 43 ++--
arch/arm/boot/dts/at91sam9g45.dt
On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
> On Tue, 14 May 2013, Javi Merino wrote:
>
> > On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> >
> > > +static inline void init_cpu_port(struct cpu_port *port, u32 index, u32
> > > mpidr)
> >
> > The mpidr shou
HI,
v2:
use common IRQ define
split patch
rebase on 3.10-rc1
The follow patch series switch the at91 to DT pre-processor
So we can use macro for AIC and Pinctrl instead of magic
The following changes since commit f722406faae2d073cc1d01063d1123c
HI,
v2:
use common IRQ define
split patch
rebase on 3.10-rc1
The follow patch series switch the at91 to DT pre-processor
So we can use macro for AIC and Pinctrl instead of magic
The following changes since commit f722406faae2d073cc1d01063d1123c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
---
include/dt-bindings/pinctrl/at91.h | 35 +++
1 file changed, 35 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/at91.h
diff --git a/include/dt-bindings/pinctrl/at91.h
b/include
Hi Laurent
Thanks for your work on this! Sorry for jumping in so late in the game.
Let's do it this way: I don't think my comments are serious enough to
enforce a v4. If noone else complains, I'm fine with addressing them in an
incremental patch. If you get more comments and have to do a v4, yo
Now that we have the necessary drivers and Device Tree informations to
support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI
option.
Also, since the Armada 370 Mirabox has a built-in USB XHCI controller
connected on the PCIe bus, enable the corresponding options as well.
Signed-off-by:
Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
Signed-off-by: Thomas Petazzoni
---
arch/arm/mach-mvebu/Kconfig |2 ++
1 file changed, 2 ins
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PC
The current revision of the datasheet only mentions the gatable clocks
for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
interfaces. After confirmation with Marvell engineers, this patch adds
the missing gatable clocks for tho
The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: Thomas Petazzoni
Cc: Mike Turquette
---
drivers/clk/mvebu
From: Thierry Reding
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding
---
drivers/of/of_pci.c| 25 +
include/linux/of_pci.h |1 +
2 files changed, 26 insertions(+)
dif
From: Thierry Reding
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry Reding
Signed-off-by: Thomas Petazz
Hello,
This series of patches introduces PCIe support for the Marvell Armada
370 and Armada XP. It has been rebased on top of 3.10-rc1, uses the
latest of/pci code from Andrew Murray, fixes the build failure that
was detected on powerpc64, and a regression that was introduced
between the v7 and th
From: Andrew Murray
This patch factors out common implementation patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This will make it easier to w
Since 82a682676 ('ARM: dts: mvebu: Convert all the mvebu files to use
the range property') all the device nodes of Armada 370/XP are under a
common 'ranges' property that translates the device register addresses
into their absolute address, thanks to the base address of the
internal register space.
Hi Prabhakar,
Thank you for the patch.
On Wednesday 15 May 2013 18:22:29 Lad Prabhakar wrote:
> From: Lad, Prabhakar
>
> This patch adds "field-active" and "sync-on-green" as part of
> endpoint properties and also support to parse them in the parser.
>
> Signed-off-by: Lad, Prabhakar
> Cc: Ha
From: Lad, Prabhakar
This patch adds "field-active" and "sync-on-green" as part of
endpoint properties and also support to parse them in the parser.
Signed-off-by: Lad, Prabhakar
Cc: Hans Verkuil
Cc: Laurent Pinchart
Cc: Mauro Carvalho Chehab
Cc: Guennadi Liakhovetski
Cc: Sylwester Nawrocki
On Tue, May 07, 2013 at 09:11:44AM -0700, Simon Glass wrote:
> This series adjusts the image code to work with sandbox and prepares it for
> verified boot to come later.
>
> The primary goal here is to get image loading to work on sandbox, which is
> mostly a set of fairly minor changes such as u
From: Lad, Prabhakar
add OF support for the ths7303 driver.
Signed-off-by: Lad, Prabhakar
Cc: Hans Verkuil
Cc: Laurent Pinchart
Cc: Mauro Carvalho Chehab
Cc: Guennadi Liakhovetski
Cc: Sylwester Nawrocki
Cc: Sakari Ailus
Cc: Grant Likely
Cc: Rob Herring
Cc: Rob Landley
Cc: devicetree-di
This patch will allow ux500-musb to be probed and configured solely from
configuration found in Device Tree.
Cc: Felipe Balbi
Cc: Rob Herring
Cc: linux-...@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Acked-by: Linus Walleij
Acked-by: Fabio Baltieri
Signed-off-by: Lee Jones
---
..
Hi Prabhakar,
On Wednesday 15 May 2013 10:48:05 Prabhakar Lad wrote:
> On Tue, May 14, 2013 at 9:04 PM, Laurent Pinchart wrote:
> > On Tuesday 14 May 2013 16:15:34 Lad Prabhakar wrote:
> >> From: Lad, Prabhakar
> >>
> >> add OF support for the tvp7002 driver.
> >>
> >> Signed-off-by: Lad, Prabh
Without functional clock the omap_hsmmc module can't forward SDIO IRQs to
the system. This patch reconfigures dat1 line as a gpio while the fclk is
off. When the fclk is present it uses the standard SDIO IRQ detection of
the module.
The gpio irq is managed via the 'disable_depth' ref counter of th
PSTATE shows current state of data lines.
Signed-off-by: Andreas Fenkart
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 2b2ec09..61c0254 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -53,6 +53,7 @@
#define OMAP_HSMMC_RSP54
Signed-off-by: Andreas Fenkart
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 4db8de5..2b2ec09 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -224,6 +224,7 @@ struct omap_hsmmc_host {
struct pinctrl *pinctrl;
No changes to the patches itself.
Only the dependency on some omap-gpio enable_irq/disable_irq patch
has been removed.
While developing, I was struck by a bug with disable_irq. After reviewing
the disable_irq code path, I thought the interrrupt got never disabled
for omap. After fixing the bug I
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