On Tue, May 21, 2013 at 01:40:04PM +0200, Laurent Pinchart wrote:
> Hello,
>
> Here's the second version of the gpio-rcar driver DT bindings. I've tested the
> patches on the Marzen board (r8a7779).
>
> Once again I'd appreciate feedback on the DT bindings. I'm particularly
> wondering whether ge
On Fri, May 24, 2013 at 11:13:03AM +0200, Guennadi Liakhovetski wrote:
> To disable spurious interrupts, that get triggered on certain hardware, the
> irqpin driver masks them on the parent interrupt controller. To specify
> such broken devices a .control_parent parameter can be provided in the
> p
Huang Shijie, sorry for not catching this earlier, but based on my reading of
Table 4-1 of Rev. 1 of IMX6DQRM, I would use the following:
pinctrl_weim_nor_1: weim_norgrp-2 {
fsl,pins = <
[ . . . ]
On 05/24/2013 07:13 PM, Russell King - ARM Linux wrote:
Do you really want that on ARM? Given the fiasco with the location of
the registers, are you sure you want to place more trust in that
direction? Does it give you a warm fuzzy feeling to know that you
might have to work out some way to pat
On Fri, May 24, 2013 at 01:01:25PM -0400, Jason Cooper wrote:
> On Fri, May 24, 2013 at 01:03:25PM +0200, Linus Walleij wrote:
> > IMO: if you want to go down that road, what you really want is not
> > ever more expressible device trees, but real open firmware,
> > or ACPI or UEFI that can interpre
On Fri, May 24, 2013 at 01:03:25PM +0200, Linus Walleij wrote:
> On Fri, May 24, 2013 at 12:40 AM, Sebastian Hesselbarth
> wrote:
> > On 05/23/2013 08:40 PM, Jason Cooper wrote:
>
> >> I think marvell,psc1_reset =<>; gives us the most flexibility in
> >> accurately describing the hardware.
> >
>
Add a GPIO driver for the low-power Powerdown Controller GPIOs in the
TZ1090 SoC.
The driver is instantiated by device tree and supports interrupts for
the SysWake GPIOs only.
Signed-off-by: James Hogan
Cc: Grant Likely
Cc: Rob Herring
Cc: Rob Landley
Cc: Linus Walleij
Cc: linux-...@vger.ker
Add a GPIO driver for the main GPIOs found in the TZ1090 (Comet) SoC.
This doesn't include low-power GPIOs as they're controlled separately
via the Powerdown Controller (PDC) registers.
The driver is instantiated by device tree and supports interrupts for
all GPIOs.
Signed-off-by: James Hogan
Cc
Add a pin control driver for the TZ1090's low power pins via the
powerdown controller SOC_GPIO_CONTROL registers.
These pins have individually controlled pull-up, and group controlled
schmitt, slew-rate, drive-strength, and power-on-start (pos).
The pdc_gpio0 and pdc_gpio1 pins can also be muxed
Add really minimal support for Toumaz Xenif TZ1090 SoC (A.K.A. Comet).
This consists of minimal build infrastructure, device tree files, and a
defconfig based on meta2_defconfig.
This SoC contains a 2-threaded HTP (Meta 2) as the main application
processor, and is found in a number of development
Add irqchip driver for the ImgTec PowerDown Controller (PDC) as found in
the TZ1090. The PDC has a number of general system wakeup (SysWake)
interrupts (which would for example be connected to a power button or an
external peripheral), and a number of peripheral interrupts which can
also wake the s
If no init_machine callback is provided, call of_platform_populate()
instead. This allows a board/SoC that only needs to call
of_platform_populate to omit the callback altogether.
Signed-off-by: James Hogan
Cc: Grant Likely
Cc: Rob Herring
Cc: Arnd Bergmann
Cc: devicetree-discuss@lists.ozlabs.
The Toumaz Xenif TZ1090 SoC (AKA Comet) contains a 2-threaded
Linux-capable HTP (Meta 2), and is found in a number of development
boards and digital radios, such as the Minimorph Development Platform.
This patchset adds some core infrastructure for the TZ1090, including
drivers for the powerdown c
On 23/05/13 22:44, Arnd Bergmann wrote:
Thankyou Arnd for extending this discussion.
> On Monday 20 May 2013, Srinivas KANDAGATLA wrote:
>> On 17/05/13 15:36, Arnd Bergmann wrote:
>>
>> On the other hand using device trees to describe the HW
>> configuration(sysconfs) made more sense and got rid of
On 05/24/2013 01:30 AM, Alex Courbot wrote:
> On 05/24/2013 01:27 AM, Stephen Warren wrote:
>>> Stephen, please note that the "r5g6b5" mode initially supported
>>> by the driver becomes "b5g6r5" with the new function. This is because
>>> the least significant bits are defined first in the string -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: net...@vger.kernel.org
---
.../devicetree/bindings/net/micrel-ks8851.txt |9 ++
drivers/net/ethernet/micrel/ks8851_mll.c | 33 +++-
2 files changed, 35 insertions(+), 7 deletions(-)
create mode 100644 Do
This patch series adds driver for palmas usb which is used to detect
attach/detach events of usb device and usb host.
[PATCH v5 2/3] extcon: Palmas Extcon Driver which was sent previously
is added in this patch series itself. The revision history is added
in the patch comments section.
A checkpat
Modified dwc3-omap to receive connect and disconnect notification using
extcon framework. Also did the necessary cleanups required after
adapting to extcon framework.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/usb/dwc3/dwc3-omap.c | 80 +--
include
From: Graeme Gregory
This is the driver for the USB comparator built into the palmas chip. It
handles the various USB OTG events that can be generated by cable
insertion/removal.
Signed-off-by: Graeme Gregory
Signed-off-by: Moiz Sonasath
Signed-off-by: Ruchika Kharwar
Signed-off-by: Kishon Vi
From: Graeme Gregory
Added an API to set/clear the switch bit on SMPS10 which can be used by
palmas usb. The switch bit should be set in order for palmas to
supply VBUS and is needed when OMAP is acting as USB HOST.
Signed-off-by: Graeme Gregory
Signed-off-by: Kishon Vijay Abraham I
---
drive
The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power Controller
(SPC), contains several memory mapped registers to control among
In case some transactions to the Serial Power Controller (SPC) are lost owing
to multiple operations handled at once by the M3 controller the OS needs to
rely on a configuration API that can time out so that failures do not result
in an unusable system.
This patch adds a timeout API to the vexpres
On Fri, 24 May 2013, Linus Walleij wrote:
> On Fri, May 24, 2013 at 10:27 AM, Lee Jones wrote:
> > On Fri, 24 May 2013, Linus Walleij wrote:
> >> From: Linus Walleij
> >>
> >> Commits:
> >> "ARM: ux500: Add Device Tree nodes for the ux500 Crypt device"
> >> "ARM: ux500: Add Device Tree nodes for
From: Pawel Moll
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates the bridge functio
This patch series introduces support for the Versatile Express Serial
Power Controller (SPC) present in ARM Versatile Express TC2 core tiles.
SPC driver is a fundamental component of TC2 power management and allows
to carry out C-state management and DVFS for A15 and A7 clusters.
First two patches
Hi Linus,
On Fri, May 24, 2013 at 5:59 PM, Linus Walleij wrote:
> On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart
> wrote:
>
>> Reference the st1232 reset GPIO from the device tree and remove it from
>> board code.
>>
>> Signed-off-by: Laurent Pinchart
>
>> +++ b/arch/arm/boot/dts/r8a7740-arm
On Fri, May 10, 2013 at 9:31 PM, Javier Martinez Canillas
wrote:
> The IGEPv2 board has an 512MB NAND flash memory.
>
> Add a device node for this NAND and its parition layout.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> Benoit,
>
> This patch depends on a previous posted patch:
>
> [PA
On Fri, May 24, 2013 at 10:32 AM, Lee Jones wrote:
> On Fri, 24 May 2013, Linus Walleij wrote:
>> On Thu, May 16, 2013 at 1:27 PM, Lee Jones wrote:
>>
>> > By providing an OF match table with a suitable compatible string, we
>> > can ensure the ux500-crypt driver is probed by supplying an associa
On Fri, May 24, 2013 at 10:27 AM, Lee Jones wrote:
> On Fri, 24 May 2013, Linus Walleij wrote:
>> From: Linus Walleij
>>
>> Commits:
>> "ARM: ux500: Add Device Tree nodes for the ux500 Crypt device"
>> "ARM: ux500: Add Device Tree nodes for the ux500 Hash device"
>>
>> Added the crypto and hash d
Prabhakar,
On 05/16/2013 03:18 PM, Lad Prabhakar wrote:
From: Lad, Prabhakar
This patch adds "sync-on-green" property as part of
endpoint properties and also support to parse them in the parser.
--- a/Documentation/devicetree/bindings/media/video-interfaces.txt
+++ b/Documentation/devicetre
On Fri, May 24, 2013 at 12:40 AM, Sebastian Hesselbarth
wrote:
> On 05/23/2013 08:40 PM, Jason Cooper wrote:
>> I think marvell,psc1_reset =<>; gives us the most flexibility in
>> accurately describing the hardware.
>
>
> IMHO using that is just another workaround for a broken driver. We
> could
Enable the WEIM NOR for imx6q{dl} boards.
For the pin conflict with SPI NOR, its status is set to "disabled".
Signed-off-by: Huang Shijie
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/i
Add two pinctrls for WEIM:
one for the weim nor, another for the chipselect.
Signed-off-by: Huang Shijie
---
arch/arm/boot/dts/imx6dl.dtsi | 60 +
1 files changed, 60 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm
Add two pinctrls for WEIM:
one for the weim nor, another for the chipselect.
Signed-off-by: Huang Shijie
---
arch/arm/boot/dts/imx6q.dtsi | 61 ++
1 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/
Add the clock and compatible information for the weim.
Also adds the weim label.
Signed-off-by: Huang Shijie
---
arch/arm/boot/dts/imx6qdl.dtsi |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 42e461
In the imx6q-sabreauto and imx6dl-sabreauto boards,
the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but
it is used as a data pin for the WEIM NOR.
In order to fix the conflict, this patch removes the pin from the hog,
and adds a new board-level pinctrl: pinctrl_ecspi1_sabreauto.
The S
The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.
In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
This patch also adds the devicetree binding document.
The driver only works when the devicetree is enabl
This patch set adds a new driver for WEIM in the imx6q{dl}-sabreauto boards.
The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.
In the case of i.MX6q-sabreauto, only the NOR is connected to WEIM.
v2 --> v3:
[0
On 15:42 Thu 23 May , Stephen Warren wrote:
> On 05/19/2013 03:17 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> ...
> > how a pin can not have mux?
>
> Well, if that's the way HW is designed, that's just the way it is.
>
> There are certainly pins on Tegra which don't have a mux in HW, but ha
Hi Linus,
On Fri, May 24, 2013 at 11:23:04AM +0200, Linus Walleij wrote:
> On Thu, May 23, 2013 at 11:32 AM, Wei Yongjun wrote:
>
> > From: Wei Yongjun
> >
> > Fix to return a negative error code from the devm_clk_get() error
> > handling case instead of 0, as done elsewhere in this function.
>
On Thu, May 23, 2013 at 11:32 AM, Wei Yongjun wrote:
> From: Wei Yongjun
>
> Fix to return a negative error code from the devm_clk_get() error
> handling case instead of 0, as done elsewhere in this function.
>
> Introduced by commit 950707c0eb5c7aeaa2c446a04c824f4be686d2f6
> (pinctrl: sunxi: ad
On Wed, May 22, 2013 at 4:28 PM, Christian Ruppert
wrote:
> On Mon, May 20, 2013 at 10:10:33AM +0200, Linus Walleij wrote:
>> It's not even pinctrl-simple-centric it is completely generic.
>> The code is in drivers/gpio/gpiolib-of.c.
>>
>> It was written by Shiraz Hashin and Haojian Zhuang.
>> At
In the non-DT case all interrupts get mapped statically during probing,
therefore, if a spurious interrupt arrives, it can easily be mapped back
to hardware registers and bits and handled. In the DT case interrupts are
mapped only when a device, using that interrupt is instantiated from DT.
So, spu
To disable spurious interrupts, that get triggered on certain hardware, the
irqpin driver masks them on the parent interrupt controller. To specify
such broken devices a .control_parent parameter can be provided in the
platform data. In the DT case we need a property, to do the same.
Signed-off-by
On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash
wrote:
> Based function-mask and submask preoperties patch allocates and registers
> pins.
> Patch is fixes the issue reported and discussed here:
> http://www.spinics.net/lists/arm-kernel/msg235213.html
I'd like Tony to ACK this, and Haoj
On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart
wrote:
> Reference the st1232 reset GPIO from the device tree and remove it from
> board code.
>
> Signed-off-by: Laurent Pinchart
> +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
> @@ -43,6 +43,7 @@
> interrupts =
On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart
wrote:
> Support device instantiation through the device tree. The compatible
> property is used to select the SoC pinmux information.
>
> Set the gpio_chip device field to the PFC device to enable automatic
> GPIO OF support.
>
> Cc: devicetree-d
On Fri, 24 May 2013, Linus Walleij wrote:
> From: Linus Walleij
>
> Commits:
> "ARM: ux500: Add Device Tree nodes for the ux500 Crypt device"
> "ARM: ux500: Add Device Tree nodes for the ux500 Hash device"
>
> Added the crypto and hash devices conditionally, i.e. so as to
> be turned on per-boa
On 24/05/2013 00:59, Jean-Christophe PLAGNIOL-VILLARD :
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre
Acked-by: Nicolas Ferre
Stacked on at91-3.10-fixes. Thanks.
---
arch/arm/boot/dts/at91sam9n12.dtsi |1 +
arch/arm/mach-at91/at91sam9n12.c |6 --
2 f
On Tue, May 21, 2013 at 2:14 PM, Laurent Pinchart
wrote:
> Platform data isn't used, support can thus be removed.
>
> Signed-off-by: Laurent Pinchart
Acked-by: Linus Walleij
Yours,
Linus Walleij
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devicetree-discuss
On 05/24/2013 01:27 AM, Stephen Warren wrote:
Stephen, please note that the "r5g6b5" mode initially supported
by the driver becomes "b5g6r5" with the new function. This is because
the least significant bits are defined first in the string - this
makes parsing much easier, notably for modes which
On Fri, May 24, 2013 at 03:16:53PM +0800, Huang Shijie wrote:
> 于 2013年05月23日 21:09, Arnd Bergmann 写道:
> >OTOH, I agree that it would be nicer if the clk could remain turned
> >off as long as no children are active. Can we do a clk_disable()
> >after setting up the timings for the children and then
于 2013年05月23日 21:09, Arnd Bergmann 写道:
OTOH, I agree that it would be nicer if the clk could remain turned
off as long as no children are active. Can we do a clk_disable()
after setting up the timings for the children and then expect those
to actually start up the clk again when they need it?
Or
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