Quoting Tero Kristo (2013-06-04 06:28:54)
Hi Mike,
On Mon, 2013-06-03 at 23:39 -0700, Mike Turquette wrote:
This is a very incomplete conversion of a handful of OMAP4 PRCM clocks
from the statically defined clock data in
arch/arm/mach-omap2/cclock44xx_data.c to a new dts file in
On Tue, Jun 4, 2013 at 2:05 PM, Heiko Stübner he...@sntech.de wrote:
+PULL_AUTO (1 0): indicate this pin needs a pull setting for SoCs
+ that determine the pull up or down themselfs
Hm, never saw that before...
Citing the original gpio driver:
/*
Dear Heiko Stübner,
On Mon, 3 Jun 2013 01:02:20 +0200, Heiko Stübner wrote:
index 000..a2d8c70
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-$(CONFIG_ARCH_ROCKCHIP) := 0x60408000
+params_phys-$(CONFIG_ARCH_ROCKCHIP) := 0x60088000
Hi Russell,
On 3/6/2013 9:45 PM, Matt Porter wrote:
Move mach-davinci/dma.c to common/edma.c so it can be used
by OMAP (specifically AM33xx) as well.
Signed-off-by: Matt Porter mpor...@ti.com
Acked-by: Sekhar Nori nsek...@ti.com
Can you please ack this movement of davinci private EDMA
On Fri, May 31, 2013 at 20:25:38, Strashko, Grygorii wrote:
On 05/31/2013 01:13 PM, Hebbar Gururaja wrote:
Amend the I2C omap pin controller to optionally take a pin control
handle and set the state of the pins to:
- default on boot, resume and before performing an i2c transfer
- idle
On 06/04/13 22:53, Gerlando Falauto wrote:
thanks for your answer and your hard work about this whole cleanup.
Two more questions though -- the whole pulling sequence and the
mainlining process is still very confusing to me so I really have no
idea where to look or what to expect.
1) Has this
Hi Geraldo,
On 06/05/2013 11:37 AM, Gerlando Falauto wrote:
Hi Sebastian,
thanks for the info.
On 06/05/2013 11:04 AM, Sebastian Hesselbarth wrote:
[...]
I have irqchip and clocksource drivers ready for Orion SoCs (Kirkwood,
Dove, Orion5x, MV78x00). Just need some time to rebase and
On 06/05/13 11:37, Gerlando Falauto wrote:
On 06/05/2013 11:04 AM, Sebastian Hesselbarth wrote:
[...]
I have irqchip and clocksource drivers ready for Orion SoCs (Kirkwood,
Dove, Orion5x, MV78x00). Just need some time to rebase and send patches.
[sorry we've moved to a different topic]
Jingoo Han wrote:
On Wednesday, May 08, 2013 3:02 PM, Vikas Sajjan wrote:
Adds clock provider information for DP controller required by CCF.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Signed-off-by: Arun Kumar K arun...@samsung.com
Hi Vikas Sajjan,
Acked-by: Jingoo Han
Jingoo Han wrote:
On Wednesday, May 08, 2013 3:02 PM, Vikas Sajjan wrote:
Add DT node for DP controller to exynos5250 based Arndale Board
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Hi Vikas Sajjan,
Reviewed-by: Jingoo Han jg1@samsung.com
Applied, thanks.
- Kukjin
On 5/28/2013 1:58 PM, Manjunathappa, Prakash wrote:
1) struct davinci_uart_config is introduced to specify
UART ports brought out or enabled on the board. But
none of the boards use them for that purpose, so clean
it up.
2) Have pointer to platform device as a argument for
Kukjin Kim wrote:
Jingoo Han wrote:
On Wednesday, May 08, 2013 3:02 PM, Vikas Sajjan wrote:
Add DT node for DP controller to exynos5250 based Arndale Board
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Hi Vikas Sajjan,
Reviewed-by: Jingoo Han jg1@samsung.com
The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power Controller
(SPC), contains several memory mapped registers to control among
From: Pawel Moll pawel.m...@arm.com
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates
On Wed, Jun 05, 2013 at 04:21:41PM +0800, Nicolin Chen wrote:
Looks pretty good, a few comments but they're all fairly minor.
+ WM8962 pins:
+ * HPOUTL
+ * HPOUTR
+ * SPKOUTL
+ * SPKOUTR
+ * MICBIAS
+ * IN3R
+ * DMIC
+ * DMICDAT
No need to list all these, just reference the
On Wed, Jun 05, 2013 at 02:39:57PM +0300, Illia Smyrnov wrote:
+SPI Controller specific data in SPI slave nodes:
+- The spi slave nodes can provide the following information which is used
+ by the spi controller:
+ - ti,spi-turbo-mode: Set turbo mode for this device.
+
What is turb mode
On Wed, Jun 05, 2013 at 02:39:58PM +0300, Illia Smyrnov wrote:
- The spi slave nodes can provide the following information which is used
by the spi controller:
- ti,spi-turbo-mode: Set turbo mode for this device.
+ - ti,spi-fifo-depth: Enable FIFO and set up buffer depth.
Why is this
On Wed, Jun 05, 2013 at 08:12:55PM +0800, Nicolin Chen wrote:
struct wm8962_priv {
+ struct wm8962_pdata *pdata;
More idiomatic style for this is to just embed a copy of the platform
data struct in the private data then copy any driver model platform data
on top of it. This simplifies
On Wed, Jun 05, 2013 at 08:12:56PM +0800, Nicolin Chen wrote:
+ - gpio-cfg : A list of GPIO configuration register values. The list must
+be 6 entries long. If absent, no configuration of these registers is
+performed. And note that the max value for each entry is 0x, don't
+
Hi Alexander,
On Fri, May 31, 2013 at 08:38:44PM +0200, Michael Grzeschik wrote:
From: Michael Grzeschik m.grzesc...@pengutronix.de
The pdata structure gets copied anyway inside ci13xxx_add_device
by platform_device_add. We don't need to have it static.
Signed-off-by: Michael Grzeschik
Sachin Kamat wrote:
These nodes have separately been added to 4212 and 4412 dtsi
files by commit 30269ddff1 (ARM: exynos: add missing properties
for combiner IRQs). The existing node also contained a few
incorrect entries.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
Patch
On Tue, Jun 4, 2013 at 8:15 PM, Kevin Hilman khil...@linaro.org wrote:
[Me]
I think this will save a *lot* of identical code in all the
drivers, that will just have to call
pinctrl_select_pm_sleep(), pinctrl_select_pm_default()
pinctrl_select_pm_idle() instead of all the complex code.
This
+ Afzal,
Hi Vaibhav and Afzal,
Can someone test this series before I pull it. I still don't have any AM
board to do it myself :-(
In theory, it should be fine since Florian already checked the diff, but
just in case.
Thanks,
Benoit
On 06/03/2013 04:12 PM, Florian Vaussard wrote:
Hello,
Michael Grzeschik m...@pengutronix.de writes:
Hi Alexander,
On Fri, May 31, 2013 at 08:38:44PM +0200, Michael Grzeschik wrote:
From: Michael Grzeschik m.grzesc...@pengutronix.de
The pdata structure gets copied anyway inside ci13xxx_add_device
by platform_device_add. We don't need to have
Gerlando,
On Wed, Jun 05, 2013 at 11:04:38AM +0200, Sebastian Hesselbarth wrote:
On 06/04/13 22:53, Gerlando Falauto wrote:
...
Sorry, I am really more than lost when it's about tracking
how/where/when changes are pulled. Any mainlining for dummies pointer
would be more than appreciated.
On Wed, 5 Jun 2013, Lorenzo Pieralisi wrote:
From: Pawel Moll pawel.m...@arm.com
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
On 06/03/13 7:59 AM, Heiko Stübner wrote:
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.
There also seem to be no other modifications (additional register etc)
present, so to keep the
On 06/03/13 2013 7:58 AM, Heiko Stübner wrote:
dw_mci_pltfm_remove gets exported and used by dw_mmc-exynos, so should
not be static.
Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Seungwon Jeon tgih@samsung.com
Thanks,
Seungwon Jeon
On Wed, 5 Jun 2013, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power Controller
(SPC),
Am Mittwoch, 5. Juni 2013, 16:00:43 schrieb Seungwon Jeon:
On 06/03/13 7:59 AM, Heiko Stübner wrote:
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.
There also seem to be no other
On Wed, 5 Jun 2013, Lorenzo Pieralisi wrote:
This patch is v2 of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/170624.html
V2 changes:
- Dropped timeout interface patch
- Converted interfaces to non-timeout ones, integrated and retested
- Removed
* Wei Yongjun weiyj...@gmail.com [130604 19:10]:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
The dereference to 'up' should be moved below the NULL test.
Introduced by commit ddd85e225c8885b5e4419b0499ab27100e7c366a
(serial: omap: prevent runtime PM for no_console_suspend)
Acked-by:
* Mugunthan V N mugunthan...@ti.com [130530 01:14]:
On 5/28/2013 7:35 PM, Mugunthan V N wrote:
On 5/28/2013 3:06 AM, Tony Lindgren wrote:
* Mugunthan V N mugunthan...@ti.com [130526 11:28]:
From: Hebbar Gururaja gururaja.heb...@ti.com
Amend cpsw controller to optionally take a pin control
On Wed, 2013-06-05 at 12:46 +0100, Lorenzo Pieralisi wrote:
[...]
+
+static bool __init __vexpress_spc_check_loaded(void);
+static bool (*spc_check_loaded)(void) = __vexpress_spc_check_loaded;
We get a section mismatch warning from the above because
__vexpress_spc_check_loaded is marked
On 6/5/2013 9:19 PM, Tony Lindgren wrote:
* Mugunthan V N mugunthan...@ti.com [130530 01:14]:
On 5/28/2013 7:35 PM, Mugunthan V N wrote:
On 5/28/2013 3:06 AM, Tony Lindgren wrote:
* Mugunthan V N mugunthan...@ti.com [130526 11:28]:
From: Hebbar Gururaja gururaja.heb...@ti.com
Amend cpsw
On 06/03/2013 09:36 AM, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Previously, the #line parsing regex ended with ({WS}+[0-9]+)?. The {WS}
could match line-break characters. If the #line directive did not contain
the optional flags field at the end, this could cause any
This patch series adds the following features
* Adding pinctrl PM support for CPSW and MDIO for Power Optimization
* Adding phy address to the CPSW node for EVMsk board
Changes from initial version
* Fixed the multiline function call indentation as per David Miller
recommendation.
Changes from
From: Hebbar Gururaja gururaja.heb...@ti.com
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- default on boot, resume
- sleep on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of
Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this
On 06/04/2013 02:41 AM, J Keerthy wrote:
From: Graeme Gregory g...@slimlogic.co.uk
Add the various binding files for the palmas family of chips. There is a
top level MFD binding then a seperate binding for regulators IP blocks on
chips.
diff --git
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- default on boot, resume
- sleep on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a
On 06/05/2013 01:01 AM, Linus Walleij wrote:
On Tue, Jun 4, 2013 at 2:05 PM, Heiko Stübner he...@sntech.de wrote:
...
The only problem is the pull stuff mentioned above that is either pull up or
down without the driver having knowledge about it. And generic_pinconf only
knows about them
Am Mittwoch, 5. Juni 2013, 19:18:49 schrieb Stephen Warren:
On 06/05/2013 01:01 AM, Linus Walleij wrote:
On Tue, Jun 4, 2013 at 2:05 PM, Heiko Stübner he...@sntech.de wrote:
...
The only problem is the pull stuff mentioned above that is either pull
up or down without the driver having
On Wed, Jun 05, 2013 at 10:38:15PM +0530, Mugunthan V N wrote:
From: Hebbar Gururaja gururaja.heb...@ti.com
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- default on boot, resume
- sleep on suspend()
Linus Walleij posted some patches
On 06/04/2013 03:32 PM, Tejun Heo wrote:
Hello, Mark.
On Tue, Jun 04, 2013 at 10:09:41AM -0500, Mark Langsdorf wrote:
And tell ahci core sizeof(ecx_host_priv) some way, but really, just
having a plain pointer should be enough, I think.
I think I want to do the opposite. For 90% of the AHCI
On Wed, Jun 5, 2013 at 3:46 PM, Luke Kenneth Casson Leighton
l...@lkcl.netwrote:
On Fri, May 31, 2013 at 3:52 AM, Ben Hutchings b...@decadent.org.uk
wrote:
The 3.8.y branch is over, so I think we have to move to 3.9, ready or
not. I merged the work in progress from trunk to sid and am
On Wed, Jun 5, 2013 at 3:46 PM, Luke Kenneth Casson Leighton
l...@lkcl.net wrote:
On Fri, May 31, 2013 at 3:52 AM, Ben Hutchings b...@decadent.org.uk wrote:
The 3.8.y branch is over, so I think we have to move to 3.9, ready or
not. I merged the work in progress from trunk to sid and am
On 06/05/2013 02:46 PM, jonsm...@gmail.com wrote:
On Wed, Jun 5, 2013 at 3:46 PM, Luke Kenneth Casson Leighton
l...@lkcl.net mailto:l...@lkcl.net wrote:
...
the detect line, which is the write-protect line, to setting the DRAM
clock timings, saying which kernel driver must be loaded to
On Wed, Jun 05, 2013 at 03:00:13PM -0600, Stephen Warren wrote:
2) Having U-Boot itself read a DT and configure itself, just like the
kernel does. This is relatively new, and only supported by a few boards
(all Tegra to some extent, and a couple each Samsung Exynos and Xilinx
boards). I
Hi Thomas,
On Wed, Jun 05, 2013 at 09:11:19AM +0200, Thomas Petazzoni wrote:
Dear Heiko Stübner,
On Mon, 3 Jun 2013 01:02:20 +0200, Heiko Stübner wrote:
index 000..a2d8c70
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-$(CONFIG_ARCH_ROCKCHIP)
On Wed, Jun 05, 2013 at 10:24:15PM +0100, Luke Kenneth Casson Leighton wrote:
https://github.com/linux-sunxi/u-boot-sunxi
And Then Some, stephen. there are two versions of u-boot being used:
one is the community-assembled [GPL-compliant] one, and the other
includes a
Hi Luke,
On Wednesday 05 of June 2013 22:15:08 Luke Kenneth Casson Leighton wrote:
[i've just received word, please remove debian-release from
discussions!]
On Wed, Jun 5, 2013 at 9:46 PM, jonsm...@gmail.com jonsm...@gmail.com
wrote:
Why don't you try converting the sunxi code over to
* Manjunathappa, Prakash prakash...@ti.com [130521 07:13]:
Add support to configure multiple pins in each register, existing
implementation added by [1] does not support full fledge multiple pin
configuration in single register, reports a pin clash when different
modules configure different
On Wed, Jun 05, 2013 at 05:38:45PM -0400, Lennart Sorensen wrote:
I haven't personally dealt with any nvidia arm devices, so I have no
idea how those are turning out, nor have I looked much at the marvell
ones yet (even though I have a cubox sitting on my desk I intend to play
around with).
On Wednesday 05 of June 2013 16:48:27 jonsm...@gmail.com wrote:
On Wed, Jun 5, 2013 at 3:46 PM, Luke Kenneth Casson Leighton
l...@lkcl.net wrote:
On Fri, May 31, 2013 at 3:52 AM, Ben Hutchings b...@decadent.org.uk
wrote:
The 3.8.y branch is over, so I think we have to move to 3.9, ready
On Wednesday 05 of June 2013 22:16:37 Russell King - ARM Linux wrote:
On Wed, Jun 05, 2013 at 03:00:13PM -0600, Stephen Warren wrote:
2) Having U-Boot itself read a DT and configure itself, just like the
kernel does. This is relatively new, and only supported by a few
boards
(all Tegra to
Highbank supports SGPIO by bit-banging out the SGPIO signals over
three GPIO pins defined in the DTB. Add support for this SGPIO
functionality.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2:
Added plat_data to ahci_host_priv
Moved driver specific
On 06/05/2013 03:59 PM, Henrik Nordström wrote:
ons 2013-06-05 klockan 22:24 +0100 skrev Luke Kenneth Casson Leighton:
...
so the point is: if anyone wishes me to propose to allwinner that
they convert over to devicetree, or any other proposal which involves
significant low-level changes to
On Wed, Jun 5, 2013 at 6:47 PM, luke.leighton luke.leigh...@gmail.com wrote:
On Wed, Jun 5, 2013 at 10:59 PM, Henrik Nordström
hen...@henriknordstrom.net wrote:
and then there's the boot0 and boot1 loaders, these *do* have
no, these are not tiny. boot0 is 24KB to fit the initial
On Tue, 09 Apr 2013 00:44:05 +0200, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
On 04/09/2013 12:05 AM, Rob Herring wrote:
On 04/05/2013 02:48 AM, Javier Martinez Canillas wrote:
This means that drivers that need the IRQ type/level flags defined in
the DT won't be able
On Wednesday 05 of June 2013 23:38:52 Luke Kenneth Casson Leighton wrote:
On Wed, Jun 5, 2013 at 10:52 PM, Tomasz Figa tomasz.f...@gmail.com
wrote:
Hi Luke,
allo tomasz :)
ok - much of what you say is duplicated by what russell said, so in
effect the same reply is relevant, but
On Wed, Jun 5, 2013 at 7:26 PM, luke.leighton luke.leigh...@gmail.com wrote:
On Thu, Jun 6, 2013 at 12:07 AM, jonsm...@gmail.com jonsm...@gmail.com
wrote:
On Wed, Jun 5, 2013 at 6:47 PM, luke.leighton luke.leigh...@gmail.com
wrote:
On Wed, Jun 5, 2013 at 10:59 PM, Henrik Nordström
On Fri, 5 Apr 2013 09:48:08 +0200, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
[...]
irq_of_parse_and_map() calls to irq_create_of_mapping() which calls to
the correct xlate function handler according to #interrupt-cells
(irq_domain_xlate_onecell or
On Wed, Jun 5, 2013 at 7:26 PM, luke.leighton luke.leigh...@gmail.com wrote:
On Thu, Jun 6, 2013 at 12:07 AM, jonsm...@gmail.com jonsm...@gmail.com
wrote:
On Wed, Jun 5, 2013 at 6:47 PM, luke.leighton luke.leigh...@gmail.com
wrote:
On Wed, Jun 5, 2013 at 10:59 PM, Henrik Nordström
Hi Murali,
I believe you got a reply on the mailing list pointing you to
devicetree.org. That should have the information you need. You can also
google for the OpenFirmware PCI binding to get more information
g.
On Wed, 6 Mar 2013 17:17:06 -0500, Murali Karicheri m-kariche...@ti.com wrote:
On Thursday 06 of June 2013 00:54:02 luke.leighton wrote:
On Thu, Jun 6, 2013 at 12:40 AM, Henrik Nordström
hen...@henriknordstrom.net wrote:
tor 2013-06-06 klockan 00:26 +0100 skrev luke.leighton:
no john - they've only added it to the multiplexed sections of the
drivers which they
On Fri, 31 May 2013 11:34:49 +0200, Linus Walleij linus.wall...@linaro.org
wrote:
On Fri, May 31, 2013 at 11:30 AM, Prabhakar Lad
prabhakar.cse...@gmail.com wrote:
Hi Linus,
(...)
Can you pick this patch ?
No. I'm not a maintainer of drivers/of.
Only Grant and Rob can take changes
Am Dienstag, 4. Juni 2013, 21:22:43 schrieb Mike Turquette:
Quoting Matt Sealey (2013-06-04 10:39:53)
On Tue, Jun 4, 2013 at 12:11 PM, Stephen Boyd sb...@codeaurora.org
wrote:
On 06/03/13 10:53, Mike Turquette wrote:
+Required properties:
+- compatible : shall be divider-clock.
On Wed, Jun 05, 2013 at 11:56:43PM +0100, Luke Kenneth Casson Leighton wrote:
so there's a lot of factors which i believe the linux kernel
developers are not aware of, and haven't taken into account, and to
place blame onto the SoC vendors for not working with *you* when *you*
haven't made an
Hi Doug,
On Tue, Jun 4, 2013 at 10:49 PM, Doug Anderson diand...@chromium.org wrote:
Padmavathi,
On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna padm...@samsung.com wrote:
@@ -471,6 +477,8 @@
dmas = pdma1 12
pdma1 11;
dma-names = tx,
Hi Benoit,
On Wed, Jun 05, 2013 at 18:19:00, Cousson, Benoit wrote:
+ Afzal,
Hi Vaibhav and Afzal,
Can someone test this series before I pull it. I still don't have any AM
board to do it myself :-(
Tested-by: Afzal Mohammed af...@ti.com (am335x evm)
Regards
Afzal
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