When LDO is set to voltage up, need to do enough waiting before
it ramps up to the new voltage, and this ramp up time should be
based on the register setting.
Signed-off-by: Anson Huang
---
.../bindings/regulator/anatop-regulator.txt|8
drivers/regulator/anatop-regulator.c
-27]: vddpu
bit [28-29]: vddsoc
field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: Anson Huang
---
.../bindings/regulator/anatop-regulator.txt|8
d
-27]: vddpu
bit [28-29]: vddsoc
field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: Anson Huang
---
.../bindings/regulator/anatop-regulator.txt|8
d
[26-27]: vddpu
bit [28-29]: vddsoc
field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: Anson Huang
---
.../bindings/regulator/anatop-regulator.txt|6 +++
d