Also, link SRC to IPU via phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/imx51.dtsi | 7 +++
arch/arm/boot/dts/imx53.dtsi | 7 +++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx51
to request a framework API to issue a
reset simply by providing their struct device pointer as the most common
case.
Signed-off-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
Documentation/devicetree/bindings
This driver implements a reset controller device that toggles gpios
connected to reset pins of peripheral ICs. The delay between assertion
and de-assertion of the reset signal can be configured.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
Reviewed-by: Shawn Guo shawn@linaro.org
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/imx6q.dtsi | 1 +
arch/arm/boot/dts/imx6qdl.dtsi | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index
This patch allows to use a different regulator than LDO9 as TSIREF.
It also only turns on the regulator when there are actual measurements
to be done. It is not needed for pen detection.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/mfd/da9052-i2c.txt
Hi Fabio,
thank you for the comments.
Am Freitag, den 22.03.2013, 12:51 -0300 schrieb Fabio Estevam:
Philipp Zabel wrote:
if (!tsi-stopped) {
+ error = regulator_enable(tsi-tsiref);
+ if (error 0) {
+ dev_err(tsi-da9052-dev
This patch depends on genalloc: add devres support, allow to find
a managed pool by device, which provides the of_get_named_gen_pool
and dev_get_gen_pool functions.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Acked-By: Javier Martin javier.mar...@vista-silicon.com
Acked-by: Grant Likely
node. The corresponding platform device is then fed into
dev_get_gen_pool and the resulting gen_pool is returned.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
include/linux/genalloc.h | 15 +
lib/genalloc.c | 81
allocations.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
Changes since v8:
- Changed device tree compatible string to mmio-sram
---
Documentation/devicetree/bindings/misc/sram.txt | 16
Hi, last time I posted was a bit close to the merge window, so I'm
reposting now. Greg, Arnd, could you take the first two patches?
These patches add support to configure on-chip SRAM via device-tree
node or platform data and to obtain the resulting genalloc pool from
the struct device pointer or
Hi Stephen,
Am Freitag, den 01.03.2013, 13:00 -0700 schrieb Stephen Warren:
On 02/26/2013 04:39 AM, Philipp Zabel wrote:
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
diff --git
to request a framework API to issue a
reset simply by providing their struct device pointer as the most common
case.
Signed-off-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
Documentation/devicetree/bindings
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/imx6q.dtsi |1 +
arch/arm/boot/dts/imx6qdl.dtsi |2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
[Added Len, Pavel, Rafael, and linux-pm to Cc, as there might be some
need for integration with the PM runtime infrastructure?]
The system reset controller (SRC) on i.MX51, i.MX53, and i.MX6q controls
reset lines to the GPU, VPU, IPU, and OpenVG IP modules.
The following patches add a simple
Also, link SRC to IPU via phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/imx51.dtsi |7 +++
arch/arm/boot/dts/imx53.dtsi |7 +++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren
Request the System Reset Controller to reset the IPU if
specified via device tree phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
.../devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt|3 +++
drivers/staging/imx-drm/ipu-v3
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
Reviewed-by: Shawn Guo shawn@linaro.org
Hi,
Am Dienstag, den 19.02.2013, 14:39 -0700 schrieb Stephen Warren:
On 02/19/2013 04:35 AM, Philipp Zabel wrote:
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
I know I apparently
Am Dienstag, den 19.02.2013, 14:57 -0700 schrieb Stephen Warren:
On 02/19/2013 04:35 AM, Philipp Zabel wrote:
This driver implements a reset controller device that toggles gpios
connected to reset pins of peripheral ICs. The delay between assertion
and de-assertion of the reset signal can
Hi Shawn,
Am Sonntag, den 17.02.2013, 21:05 +0800 schrieb Shawn Guo:
On Wed, Feb 13, 2013 at 06:34:25PM +0100, Philipp Zabel wrote:
From: Stephen Warren swar...@nvidia.com
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA
Request the System Reset Controller to reset the IPU if
specified via device tree phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
.../devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt|3 +++
drivers/staging/imx-drm/ipu-v3
Also, link SRC to IPU via phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/imx51.dtsi |7 +++
arch/arm/boot/dts/imx53.dtsi |7 +++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
Changes since v2:
- Rebased onto next-20120219
---
arch/arm/boot
This driver implements a reset controller device that toggles gpios
connected to reset pins of peripheral ICs. The delay between assertion
and de-assertion of the reset signal can be configured.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v2:
- Fill
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
Changes since v2:
- Rebased onto next-20120219
---
arch/arm/boot/dts/imx6q.dtsi |1 +
arch/arm/boot/dts/imx6qdl.dtsi |2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren
to request a framework API to issue a
reset simply by providing their struct device pointer as the most common
case.
Signed-off-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
Documentation/devicetree/bindings
This patch depends on genalloc: add devres support, allow to find
a managed pool by device, which provides the of_get_named_gen_pool
and dev_get_gen_pool functions.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Acked-By: Javier Martin javier.mar...@vista-silicon.com
Acked-by: Grant Likely
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
Changes since v8:
- Changed device tree compatible string to mmio-sram
---
arch/arm/boot/dts/imx53.dtsi |5 +
arch/arm/boot/dts/imx6q.dtsi
allocations.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
Changes since v8:
- Changed device tree compatible string to mmio-sram
---
Documentation/devicetree/bindings/misc/sram.txt | 16
The system reset controller (SRC) on i.MX51, i.MX53, and i.MX6q controls
reset lines to the GPU, VPU, IPU, and OpenVG IP modules.
The following patches add a simple API for devices to request being reset
by separate reset controller hardware and implements the reset signal
device tree binding
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
Changes since v1:
- Fixed resets property in ipu2 device node.
---
arch/arm/boot/dts/imx6q.dtsi |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm
Request the System Reset Controller to reset the IPU if
specified via device tree phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
.../devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt|3 +++
drivers/staging/imx-drm/ipu-v3
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren
Also, link SRC to IPU via phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
Changes since v1:
- Changed compatible strings to fsl,soc-src
---
arch/arm/boot/dts/imx51.dtsi |7 +++
arch/arm/boot/dts/imx53.dtsi |7 +++
2
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Stephen Warren swar...@nvidia.com
---
Changes since v1:
- Added missing header
to request a framework API to issue a
reset simply by providing their struct device pointer as the most common
case.
Signed-off-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Documentation/devicetree/bindings/reset/reset.txt | 75
Hi Grant,
Am Freitag, den 08.02.2013, 20:16 + schrieb Grant Likely:
On Mon, 4 Feb 2013 12:32:16 +0100, Philipp Zabel p.za...@pengutronix.de
wrote:
This driver requests and remaps a memory region as configured in the
device tree. It serves memory from this region via the genalloc API
Am Dienstag, den 05.02.2013, 00:53 +0900 schrieb Paul Mundt:
On Mon, Feb 04, 2013 at 12:32:16PM +0100, Philipp Zabel wrote:
This driver requests and remaps a memory region as configured in the
device tree. It serves memory from this region via the genalloc API.
It optionally enables
These patches add support to configure on-chip SRAM via device-tree
node or platform data and to obtain the resulting genalloc pool from
the struct device pointer or a phandle pointing at the device tree node.
This allows drivers to allocate SRAM with the genalloc API without
hard-coding the
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
arch/arm/boot/dts/imx53.dtsi |5 +
arch/arm/boot/dts/imx6q.dtsi |6 ++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
node. The corresponding platform device is then fed into
dev_get_gen_pool and the resulting gen_pool is returned.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v7:
- Removed the global pool list. Instead, added a devres managed version of
gen_pool_create, replacing
allocations.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
Changes since v7:
- Removed obsolete __devinit/__devexit/__devexit_p
---
Documentation/devicetree/bindings/misc/sram.txt | 17
drivers/misc/Kconfig
This patch depends on genalloc: add devres support, allow to find
a managed pool by device, which provides the of_get_named_gen_pool
and dev_get_gen_pool functions.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v7:
- In the platform data case, retrieve gen_pool by device
Hi Matt,
thank you for your comments.
Am Freitag, den 18.01.2013, 13:57 -0600 schrieb Matt Sealey:
On Wed, Jan 16, 2013 at 10:13 AM, Philipp Zabel p.za...@pengutronix.de
wrote:
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules
Hi Shawn,
thank you for your comments.
Am Donnerstag, den 17.01.2013, 14:12 +0800 schrieb Shawn Guo:
On Wed, Jan 16, 2013 at 05:13:06PM +0100, Philipp Zabel wrote:
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits
Am Mittwoch, den 16.01.2013, 15:19 -0700 schrieb Stephen Warren:
On 01/16/2013 09:13 AM, Philipp Zabel wrote:
Also, link SRC to IPU via phandle.
Aside from the comments I already made, the series,
Reviewed-by: Stephen Warren swar...@nvidia.com
Thank you.
although I'm not 100% sure
Hi Stephen,
Am Mittwoch, den 16.01.2013, 15:15 -0700 schrieb Stephen Warren:
On 01/16/2013 09:13 AM, Philipp Zabel wrote:
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
diff --git
The system reset controller (SRC) on i.MX51, i.MX53, and i.MX6q controls
reset lines to the GPU, VPU, IPU, and OpenVG IP modules.
The following patches add a simple API for devices to request being reset
by separate reset controller hardware. They implement the reset signal
device tree binding
From: Stephen Warren swar...@nvidia.com
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA, ...) designs.
Such a binding would allow the creation of a reset subsystem, which
could replace APIs such as the following Tegra-specific API:
void
Also, link SRC to IPU via phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx51.dtsi |7 +++
arch/arm/boot/dts/imx53.dtsi |7 +++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx6q.dtsi |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index d6265ca..c445959 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/Kconfig |1 +
arch/arm/mach-imx/common.h |3 ++-
arch/arm/mach-imx/mach-imx6q.c
Request the System Reset Controller to reset the IPU if
specified via device tree phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt|3 +++
drivers/staging/imx-drm/ipu-v3/ipu-common.c| 12
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/Kconfig|2 +
drivers/Makefile |2 +
drivers/reset/Kconfig
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings
Hi Stephen,
Am Mittwoch, den 09.01.2013, 11:15 -0700 schrieb Stephen Warren:
On 01/09/2013 10:17 AM, Philipp Zabel wrote:
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/reset/fsl,imx-src.txt | 45
I proposed something very
Am Donnerstag, den 10.01.2013, 14:56 +0800 schrieb Shawn Guo:
Hi Philipp,
On Wed, Jan 09, 2013 at 06:17:15PM +0100, Philipp Zabel wrote:
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/reset/fsl,imx-src.txt | 45
arch/arm
Am Mittwoch, den 09.01.2013, 15:57 -0200 schrieb Fabio Estevam:
On Wed, Jan 9, 2013 at 3:53 PM, Fabio Estevam feste...@gmail.com wrote:
On Wed, Jan 9, 2013 at 3:40 PM, Philipp Zabel p.za...@pengutronix.de
wrote:
I rebased them onto next-20130109 (with this base compile-tested only
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx6q.dtsi |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index d6265ca..aac017b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/Kconfig |1 +
arch/arm/mach-imx/common.h |3 ++-
arch/arm/mach-imx/mach-imx6q.c
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/reset/fsl,imx-src.txt | 45
arch/arm/mach-imx/src.c| 41 ++
include/linux/imx-src.h|6 +++
3 files changed, 92
Also, link SRC to IPU via phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx51.dtsi |6 ++
arch/arm/boot/dts/imx53.dtsi |9 +
2 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index
The system reset controller (SRC) on i.MX51, i.MX53, and i.MX6q controls
reset lines to the GPU, VPU, IPU, and OpenVG IP modules.
The following patches allow to link modules and SRC reset lines via phandle
properties in the device tree. Drivers can then request their IP modules
to be reset by the
Request the System Reset Controller to reset the IPU if
specified via device tree phandle.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../bindings/staging/imx-drm/fsl-imx-drm.txt |3 +++
drivers/staging/imx-drm/ipu-v3/ipu-common.c| 20 +---
2
Hi Fabio,
Am Mittwoch, den 09.01.2013, 15:33 -0200 schrieb Fabio Estevam:
On Wed, Jan 9, 2013 at 3:17 PM, Philipp Zabel p.za...@pengutronix.de wrote:
The system reset controller (SRC) on i.MX51, i.MX53, and i.MX6q controls
reset lines to the GPU, VPU, IPU, and OpenVG IP modules
Hi,
Am Montag, den 26.11.2012, 18:56 +0200 schrieb Tomi Valkeinen:
On 2012-11-26 18:10, Steffen Trumtrar wrote:
Hi,
On Mon, Nov 26, 2012 at 04:38:36PM +0200, Tomi Valkeinen wrote:
+optional properties:
+ - hsync-active: hsync pulse is active low/high/ignored
+ - vsync-active:
Hi,
On Fri, 2012-11-23 at 15:24 +0100, Philipp Zabel wrote:
These patches add support to configure on-chip SRAM via device-tree
node or platform data and to obtain the resulting genalloc pool from
the physical address or a phandle pointing at the device tree node.
This allows drivers
On Tue, 2012-12-04 at 08:19 -0800, Greg Kroah-Hartman wrote:
On Tue, Dec 04, 2012 at 09:53:38AM +0100, Philipp Zabel wrote:
Hi,
On Fri, 2012-11-23 at 15:24 +0100, Philipp Zabel wrote:
These patches add support to configure on-chip SRAM via device-tree
node or platform data
These patches add support to configure on-chip SRAM via device-tree
node or platform data and to obtain the resulting genalloc pool from
the physical address or a phandle pointing at the device tree node.
This allows drivers to allocate SRAM with the genalloc API without
hard-coding the genalloc
This patch keeps all created pools in a global list and adds two
functions that allow to retrieve the gen_pool pointer from a known
physical address and from a device tree node.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
include/linux
This patch depends on genalloc: add a global pool list,
allow to find pools by phys address, which provides the
of_get_named_gen_pool function.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/media/platform/Kconfig |3 +--
drivers/media/platform/coda.c | 47
allocations.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
Documentation/devicetree/bindings/misc/sram.txt | 17
drivers/misc/Kconfig|9 ++
drivers/misc/Makefile |1
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
arch/arm/boot/dts/imx53.dtsi |5 +
arch/arm/boot/dts/imx6q.dtsi |6 ++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
Am Freitag, den 16.11.2012, 11:00 -0500 schrieb Paul Gortmaker:
On 12-11-16 10:21 AM, Philipp Zabel wrote:
Am Freitag, den 16.11.2012, 10:08 -0500 schrieb Paul Gortmaker:
On 12-11-16 05:30 AM, Philipp Zabel wrote:
This patch depends on genalloc: add a global pool list,
allow to find pools
These patches add support to configure on-chip SRAM via device-tree
node or platform data and to obtain the resulting genalloc pool from
the physical address or a phandle pointing at the device tree node.
This allows drivers to allocate SRAM with the genalloc API without
hard-coding the genalloc
This patch depends on genalloc: add a global pool list,
allow to find pools by phys address, which provides the
of_get_named_gen_pool function.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/media/platform/Kconfig |3 +--
drivers/media/platform/coda.c | 47
.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
Documentation/devicetree/bindings/misc/sram.txt | 17
drivers/misc/Kconfig|9 ++
drivers/misc/Makefile |1 +
drivers/misc/sram.c
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
arch/arm/boot/dts/imx53.dtsi |5 +
arch/arm/boot/dts/imx6q.dtsi |6 ++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
This patch keeps all created pools in a global list and adds two
functions that allow to retrieve the gen_pool pointer from a known
physical address and from a device tree node.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Reviewed-by: Shawn Guo shawn@linaro.org
---
include/linux
Am Freitag, den 16.11.2012, 10:08 -0500 schrieb Paul Gortmaker:
On 12-11-16 05:30 AM, Philipp Zabel wrote:
This patch depends on genalloc: add a global pool list,
allow to find pools by phys address, which provides the
of_get_named_gen_pool function.
Signed-off-by: Philipp Zabel p.za
Am Freitag, den 16.11.2012, 09:09 -0500 schrieb Matt Porter:
On Thu, Nov 15, 2012 at 02:11:35PM +0100, Philipp Zabel wrote:
Am Mittwoch, den 14.11.2012, 19:15 + schrieb Grant Likely:
On Thu, 18 Oct 2012 16:27:33 +0200, Philipp Zabel
p.za...@pengutronix.de wrote:
From: Matt Porter
Am Mittwoch, den 14.11.2012, 19:15 + schrieb Grant Likely:
On Thu, 18 Oct 2012 16:27:33 +0200, Philipp Zabel p.za...@pengutronix.de
wrote:
From: Matt Porter mpor...@ti.com
Adds support for setting the genalloc pool's minimum allocation
order via DT or platform data. The allocation
Hi Paul,
Am Freitag, den 26.10.2012, 15:46 -0400 schrieb Paul Gortmaker:
On Thu, Oct 18, 2012 at 10:27 AM, Philipp Zabel p.za...@pengutronix.de
wrote:
This patch keeps all created pools in a global list and adds two
functions that allow to retrieve the gen_pool pointer from a known
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