On Wednesday 03 April 2013 07:49 PM, Peter De Schrijver wrote:
On Mon, Mar 25, 2013 at 12:15:47PM +0100, Prashant Gaikwad wrote:
On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider
On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
snip
+ 263 cclk_lp
+ 264 dfll_ref
+ 265 dfll_soc
+
Peter,
branch for me to merge, obviously after 3.9-rc1 is out.
Thanks.
Prashant, could you provide a review/ack for this series too.
For the series
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
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On Monday 04 February 2013 08:04 PM, Peter De Schrijver wrote:
On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
...
+ /* xusb_hs_src */
+ val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+ val
On Monday 04 February 2013 08:02 PM, Peter De Schrijver wrote:
On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote:
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
...
-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll
-by: Prashant Gaikwad pgaik...@nvidia.com
drivers/clk/tegra/clk-pll.c | 38 --
drivers/clk/tegra/clk-tegra20.c |7 +++
drivers/clk/tegra/clk-tegra30.c |7 +++
drivers/clk/tegra/clk.h | 13 +
4 files changed, 59 insertions
.
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
drivers/clk/tegra/clk-periph.c | 11 ++-
drivers/clk/tegra/clk-tegra20.c |2 +-
drivers/clk/tegra/clk-tegra30.c |2 +-
drivers/clk/tegra/clk.h |9 ++---
4 files changed, 14 insertions(+), 10 deletions
On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote:
On 2/1/2013 5:18 AM, Peter De Schrijver wrote:
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
TEGRA_PERIPH_NO_RESET BIT(0)
#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
#define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
Comment for this flag, otherwise
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Add references to tegra_car clocks for the basic device nodes.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
arch/arm/boot/dts/tegra114.dtsi |7 ++-
1
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Implement most clocks for Tegra114. The super clocks for the CPU complex
are still missing and will be implemented in a future version.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/Makefile
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
drivers/clk/tegra/clk.c |1 +
drivers/clk/tegra/clk.h |7 +++
2 files changed, 8 insertions(+), 0
On Monday 10 September 2012 10:47 PM, Stephen Warren wrote:
On 09/09/2012 07:17 PM, Shawn Guo wrote:
On Fri, Sep 07, 2012 at 10:55:00AM -0600, Stephen Warren wrote:
Yes, that does solve the problem (well, with s/late_init/late_initcall/).
As you imply, that change wouldn't help if cpu-tegra.c
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