On Thu, 12 Apr 2012 17:10:20 -0700, David Daney ddaney.c...@gmail.com wrote:
From: David Daney david.da...@cavium.com
The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
GPIO pins, this driver handles them all. Configuring the pins as
interrupt sources is handled elsewhere
On 04/13/2012 02:56 AM, Florian Fainelli wrote:
Hi David,
[...]
+/*
+ * The address offset of the GPIO configuration register for a given
+ * line.
+ */
+static unsigned int bit_cfg_reg(unsigned int gpio)
+{
+ if (gpio 16)
+ return 8 * gpio;
+ else
+ return 8 * (gpio - 16) + 0x100;
+}
You
From: David Daney david.da...@cavium.com
The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
GPIO pins, this driver handles them all. Configuring the pins as
interrupt sources is handled elsewhere (OCTEON's irq handling code).
Signed-off-by: David Daney david.da...@cavium.com
