Hi Shawn,
thank you for your comments.
Am Donnerstag, den 17.01.2013, 14:12 +0800 schrieb Shawn Guo:
On Wed, Jan 16, 2013 at 05:13:06PM +0100, Philipp Zabel wrote:
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/Kconfig |1 +
arch/arm/mach-imx/common.h |3 ++-
arch/arm/mach-imx/mach-imx6q.c
On Wed, Jan 16, 2013 at 05:13:06PM +0100, Philipp Zabel wrote:
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/Kconfig |1 +
