[PATCH v2 1/8] dt: describe base reset signal binding

From: Stephen Warren This binding is intended to represent the hardware reset signals present internally in most IC (SoC, FPGA, ...) designs. It consists of a binding for a reset controller device (provider), and a pair of properties, "resets" and "reset-names", to link a device node (consumer) t

Re: [PATCH v2 1/8] dt: describe base reset signal binding

On Wed, Feb 13, 2013 at 06:34:25PM +0100, Philipp Zabel wrote: > From: Stephen Warren > > This binding is intended to represent the hardware reset signals present > internally in most IC (SoC, FPGA, ...) designs. > It consists of a binding for a reset controller device (provider), and a > pair of

Re: [PATCH v2 1/8] dt: describe base reset signal binding

Hi Shawn, Am Sonntag, den 17.02.2013, 21:05 +0800 schrieb Shawn Guo: > On Wed, Feb 13, 2013 at 06:34:25PM +0100, Philipp Zabel wrote: > > From: Stephen Warren > > > > This binding is intended to represent the hardware reset signals present > > internally in most IC (SoC, FPGA, ...) designs. > >