>
> > > + /* xusb_hs_src */
> > > + val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
> > > + val |= BIT(25); /* always select PLLU_60M */
> > > + writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
> > > +
> > > + clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u
On Monday 04 February 2013 08:04 PM, Peter De Schrijver wrote:
On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
...
+ /* xusb_hs_src */
+ val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+ val |=
On 02/04/2013 03:45 AM, Peter De Schrijver wrote:
> On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:
>>> + /* xusb_hs_src */
>>> + val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
>>> + val |= BIT(25); /* always select PLLU_60M */
>>> + writel(val, clk_base
On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:
> On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
...
> > + /* xusb_hs_src */
> > + val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
> > + val |= BIT(25); /* always select PLLU_60M */
> > + wri
On Mon, Feb 04, 2013 at 11:45:31AM +0100, Peter De Schrijver wrote:
> On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:
...
> > > +
> > > + /* dsia */
> > > + clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
> > > + ARRAY_
On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:
...
> > +#define RST_DEVICES_L 0x004
> > +#define RST_DEVICES_H 0x008
> > +#define RST_DEVICES_U 0x00C
> > +#define RST_DEVICES_V 0x358
> > +#define RST_DEVICES_W
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Implement most clocks for Tegra114. The super clocks for the CPU complex
are still missing and will be implemented in a future version.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/Makefile |1 +
drivers/clk/
