On Mon, May 20, 2013 at 01:11:21PM +0100, Jon Medhurst (Tixy) wrote:
On Thu, 2013-05-09 at 11:34 +0100, Lorenzo Pieralisi wrote:
[...]
+static int __init cci_probe(void)
+{
+ struct cci_nb_ports const *cci_config;
+ int ret, i, nb_ace = 0, nb_ace_lite = 0;
+ struct device_node
On Tue, 2013-05-21 at 10:21 +0100, Lorenzo Pieralisi wrote:
The node name, not type, but point is taken. I prefer to add a
compatible property to slave-if nodes (eg arm,cci-400-control-if),
I do not think that checking the node name is the standard way of
doing
things in DT world.
Thoughts
On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
On Tue, 14 May 2013, Javi Merino wrote:
On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
+static inline void init_cpu_port(struct cpu_port *port, u32 index, u32
mpidr)
The mpidr should be u64.
On Wed, 15 May 2013, Lorenzo Pieralisi wrote:
On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
On Tue, 14 May 2013, Javi Merino wrote:
On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
+static inline void init_cpu_port(struct cpu_port *port, u32
On Wed, May 15, 2013 at 03:51:43PM +0100, Nicolas Pitre wrote:
On Wed, 15 May 2013, Lorenzo Pieralisi wrote:
On Tue, May 14, 2013 at 11:21:32PM +0100, Nicolas Pitre wrote:
On Tue, 14 May 2013, Javi Merino wrote:
On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
On Tue, 14 May 2013, Javi Merino wrote:
On Thu, May 09, 2013 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
+static inline void init_cpu_port(struct cpu_port *port, u32 index, u32
mpidr)
The mpidr should be u64.
Why?
Nicolas
___
On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to
