Re: std.cpuid ARM Issue

2016-05-16 Thread safety0ff via Digitalmars-d
I don't know ARM specifics, but perhaps hwloc is useful to you: https://www.open-mpi.org/projects/hwloc/

std.cpuid ARM Issue

2016-05-16 Thread 9il via Digitalmars-d
First please see, for example, this ARM CPU http://img.deusm.com/eetimes/AMD01.png L1 cache per 1 core. L2 cache per 2 cores. L3 cache for all (8) cores. It is critical for multithread BLAS (and D BLAS is going to be the best BLAS ever) to estimate that L2 cache is per 2 cores. In the same ti