Hi,
I wonder if it is possible to tune the RF frequency in blocks writtenin c++.
In python, statementsas the followare used to tune the frequency of RF board.
r = u.tune(0, subdev, freq)
I want to adjust the receiver's RF according that of the transmitterautomatically with some frequency offset
On Mon, Jul 10, 2006 at 06:16:59PM +0800, 2 1 wrote:
Hi,
I wonder if it is possible to tune the RF frequency in blocks written in
c++.
In python, statements as the follow are used to tune the frequency of RF
board.
r = u.tune(0, subdev, freq)
I want to adjust the receiver's RF
I've built an application that intends to output both signals video and audio, but I haven't been able to test it because it requires a lot of computer power.i just added these lines:self.u = usrp.source_c(decim_rate=
options.decim,fpga_filename=self.fpga_filename) self.u_audio = copy.copy(self.u)
On Mon, Jul 10, 2006 at 03:42:12PM -0300, Augusto Pedroza wrote:
I've built an application that intends to output both signals video and
audio, but I haven't been able to test it because it requires a lot of
computer power.
i just added these lines:
self.u =
All - Do I understand correctly that gr.pll_carriertracking_cc() is
supposed to downconvert to DC? I don't see it doing that, and can't
see in the work functions where that magic would be accomplished.
Just want to make sure I'm building the most efficient graph possible.
I tried both in an
Thanks, Eric. Would you please tell me the exact C++ functions which do the tuning?
Is there any C++ class relating the usrp class in python?
hanwen2006/7/10, Eric Blossom [EMAIL PROTECTED]:
On Mon, Jul 10, 2006 at 06:16:59PM +0800, 2 1 wrote: Hi, I wonder if it is possible to tune the RF
On Tue, Jul 11, 2006 at 10:03:11AM +0800, hanwen wrote:
Thanks, Eric. Would you please tell me the exact C++ functions which do the
tuning?
You can shift the frequency by multiplying by a complex exponential.
# Local oscillator
lo = gr.sig_source_c (if_rate,# sample
Hello everybody,I am still a beginner in the project so bare with me if my questions have obvious answers.I
was looking at the verilog code for usrp_std.v module. that module
containes the tx_chain.v module which uses a module called phase_acc. I
am not sure what this later module does? It takes
