[Discuss-gnuradio] Compiling the verilog files

Hello,I would like to recompile all the verilog files for the FPGA in order to have a better understanding of the role of each module. I believe the program used to compile the files was Quartus II. Is that correct? Also, i know that Xilinx ISE can give an RTL schematic of the whole design once it

[Discuss-gnuradio] where the carrier frequency is set

Eric has already told me once that this is crazy, but I can't see any other way to do this. When Matt told  me that the RSSI circuit measures interference +/-15Mhz from the carrier, I naturally went to the code for the read_aux_adc() function in usrp_prims.{cc,h} in order to see where the carrier f

[Discuss-gnuradio] (no subject)

Can you unsubscribe me from the mailinglist. PLEASE.The tool to do that on the web site is OK, I received the email of confirmation but I don't see the change. Thank you in advance Nunien ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://l