Dear Matt,
Dear All,
Is the DDC decimate by 2 half band filter built inside the FPGA ? If it is
so, then how much the free available FPGA resources left after building all
the present USPR circuits in it? I mean, is there a free space to modify the
CIC + HBF circuit and to build a complete DDC
Eng. Firas wrote:
>
> Hi All,
>
> I'm a new USRP user. Kindly, I will be very appreciated if someone could
> tell me what is the decimation range of the USRP RX path? I'm really
> confused. Is it linear range from [1,2,3,4,.] ?or it is power of 2
> [2,4,8,16,...]?
>
> Thank you in advance
Brian Padalino wrote:
On 4/21/07, Eng. Firas <[EMAIL PROTECTED]> wrote:
Hi All,
I'm a new USRP user. Kindly, I will be very appreciated if someone
could
tell me what is the decimation range of the USRP RX path? I'm really
confused. Is it linear range from [1,2,3,4,.] ?or it is power of
On 4/21/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote:
Ok, I move the FIFOs outside next time I refactor this.
Perfect.
Yes, it makes much more sense. In the current design, the strobes are
generated by a separated block; would it be more logical to make the
strobes be generated by the tx_c
According to your diagram here:
http://gnuradio.org/trac/wiki/UsrpTxModifications
Maybe we should have a tx_usb_fifo, tx_usb_fifo_reader, tx_chan_fifo,
tx_chan_fifo reader, tx_cmd_fifo_reader (the tx_chan_fifo and
tx_cmd_fifo are essentially the same thing, but the tx_cmd_fifo_reader
should figu
On 4/21/07, Eng. Firas <[EMAIL PROTECTED]> wrote:
Hi All,
I'm a new USRP user. Kindly, I will be very appreciated if someone could
tell me what is the decimation range of the USRP RX path? I'm really
confused. Is it linear range from [1,2,3,4,.] ?or it is power of 2
[2,4,8,16,...]?
It's
Hi All,
I'm a new USRP user. Kindly, I will be very appreciated if someone could
tell me what is the decimation range of the USRP RX path? I'm really
confused. Is it linear range from [1,2,3,4,.] ?or it is power of 2
[2,4,8,16,...]?
Thank you in advance.
Firas
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I want to use the header pins J101 and J24 (on a RFX2400)to transmit and
receive serial data , Will i need to adjust the verilog codes to assign
those pins ? and would the SPI help in anyway?
I dont need to make any proceesing on that data only DDC/DUC and Rf stages.
Can some1 give me some guide
