Re: [Discuss-gnuradio] Floating point exception (core dumped)

2013-09-24 Thread NaceurElOuni
Hi again, I just realized how to pinpoint the erroneous section from gdb, by doing 'gdb --core=mycoredump ./NeoTx' >gdb run It was the "gr_diff_encoder_bb::work" which cause the exception, I am not initializing the variable of the modulus (the parameter to gr_make_diff_encoder_b

[Discuss-gnuradio] Floating point exception (core dumped)

2013-09-24 Thread NaceurElOuni
Hello list, 1/ I have been stuck into debugging process of some code, Am getting a: 'Floating point exception (core dumped)' which pop up randomly: In other words, I have tried to find out was that related really to an arithmetic error of division by zero, and I fixed all possibilities of getti

[Discuss-gnuradio] Regarding Boost message queue

2013-09-18 Thread NaceurElOuni
Hi, I am developping some source code using a boost shared pointer gr_message_sptr which is retrieving from a queue (gr_msg_queue_sptr), The issue is that when calling : gr_message_sptr mesg = queue->delete_head_nowait(); from within a while loop (BTW the queue itself is being passed from a

[Discuss-gnuradio] gr_foo_sptr (vs) gr_foo

2013-08-20 Thread NaceurElOuni
Hello, I did spent time working on GNU radio C++ API, And I was stuck debugging in some point where I need to get the gr_foo to retrieve the values of its members whereas I already instantiated gr_foo_sptr instead. Is there a way to fix this issue. Example: I already instantiated gr_msg_queue_s

Re: [Discuss-gnuradio] re-writing C/C++ or keep python coding

2013-05-27 Thread NaceurElOuni
thank you Tom -- View this message in context: http://gnuradio.4.n7.nabble.com/re-writing-C-C-or-keep-python-coding-tp41494p41619.html Sent from the GnuRadio mailing list archive at Nabble.com. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.o

[Discuss-gnuradio] re-writing C/C++ or keep python coding

2013-05-21 Thread NaceurElOuni
Hi, I do have a bunch of files written in python and C/C++ describing a complete transmission chain (Sources, Filters, Tx, Rx ...). However I am intending to add new features from the FPGA API (uhd::usrp::multi_usrp Class funtions like set_time_now()...) and those features are to be written in a

Re: [Discuss-gnuradio] getting the fpga counter for timestamping

2013-05-09 Thread NaceurElOuni
> The FPGA interprets the timestamps and waits > until the exact moment specified by the time to transmit. > The timestamps specify an absolute time on the device I would like to know what is the mechanism the FPGA is using to interpret the timestamps. You are supposing there is two time referenc

Re: [Discuss-gnuradio] getting the fpga counter for timestamping

2013-05-07 Thread NaceurElOuni
Thank you josh, I just want to be sure, are stream tags handled by timing of the FPGA (clock ticks) or the timestamps are being inserted from within the host userspace, because am getting too much variability on the latency when timestamps are inserted in the OS. regards. -- View this message

[Discuss-gnuradio] getting the fpga counter for timestamping

2013-05-07 Thread NaceurElOuni
Hi, I need to know if there is a way to retrieve a counter-like value from the FPGA to timestamp the moment I sent a packet. More precisely, I am sending a stream of packets from the host to radio, to be sent to another radio in the Rx side. Any clarifications are welcome, Regards, -- View th

Re: [Discuss-gnuradio] About "FPGA-ADC/DAC and RF frontend" Latency

2013-05-03 Thread NaceurElOuni
Hi Ben, Thanks for explanations, I've been doing some theoretical calculations on the group delay estimation and found that this part is giving negligible latency compared to the Ethernet portion between USRP and host. cheers. 2013/5/3 Naceur Amine El Ouni > Thank you Marc, > > * Ok I wil

Re: [Discuss-gnuradio] About "FPGA-ADC/DAC and RF frontend" Latency

2013-05-03 Thread NaceurElOuni
Thank you Marc, * Ok I will try using a common clock ref and input PPS * Scheduling the transmit and receive to within one tick of the 100 MHz ADC clock: Can that be done into the host GNU radio code or am supposed to move the code to the FPGA. * Is that the samples count method to get accurate

Re: [Discuss-gnuradio] Ethernet latency optimization

2013-05-02 Thread NaceurElOuni
thank you that was helpful -- View this message in context: http://gnuradio.4.n7.nabble.com/Ethernet-latency-optimization-tp41119p41123.html Sent from the GnuRadio mailing list archive at Nabble.com. ___ Discuss-gnuradio mailing list Discuss-gnuradio

[Discuss-gnuradio] Ethernet latency optimization

2013-05-02 Thread NaceurElOuni
Hi, I would like to know if having set the configuration of one USRPN210 per Ethernet interface is better (in terms of minimizing the latency towards the Host) than the configuration of multiple USRPs connected to a host via a unique Eth interface (eg. 192.168.10.x ) Which config. have better per

[Discuss-gnuradio] Target freq vs Actual freq.

2013-05-02 Thread NaceurElOuni
Hi, I am sending a stream on packets between two USRP N210, and at the Tx side i am setting a center freq. of 2.490 GHz for eg. when outputting the Tune Result, I am always getting a difference of some khz. (Target Freq: 2.49 GHz

Re: [Discuss-gnuradio] Again on the FPGA to antenna latency

2013-05-02 Thread NaceurElOuni
thank you -- View this message in context: http://gnuradio.4.n7.nabble.com/Again-on-the-FPGA-to-antenna-latency-tp41106p41108.html Sent from the GnuRadio mailing list archive at Nabble.com. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org

[Discuss-gnuradio] Again on the FPGA to antenna latency

2013-05-02 Thread NaceurElOuni
Hi all, * Is it a correct to estimate by an ICMP echo-reply the latency between a host and the USRP N210 at a giving instant. * To estimate the delay in the Digital portion from the FPGA till the signal is outputted by the antenna, is it a good way to fed the USRP by a signal (similar as am going

[Discuss-gnuradio] About "FPGA-ADC/DAC and RF frontend" Latency

2013-05-01 Thread NaceurElOuni
Hi, I am working on estimating the delay between a Tx and an Rx using a stream of packets modulated in a BPSK scheme (1 Mb/s) with a pair of N210. (Sampling of 8 Mbits/s) I want to know if the latency added by the portion(*) of [ FPGA - DAC - RF front end to the antenna *2 (Rx Part) ] could be de