Hi again,
I just realized how to pinpoint the erroneous section from gdb,
by doing 'gdb --core=mycoredump ./NeoTx'
>gdb run
It was the "gr_diff_encoder_bb::work" which cause the exception,
I am not initializing the variable of the modulus (the parameter to
gr_make_diff_encoder_b
Hello list,
1/ I have been stuck into debugging process of some code,
Am getting a: 'Floating point exception (core dumped)' which pop up
randomly:
In other words, I have tried to find out was that related really to an
arithmetic error of division by zero, and I fixed all possibilities of
getti
Hi,
I am developping some source code using a boost shared pointer
gr_message_sptr
which is retrieving from a queue (gr_msg_queue_sptr),
The issue is that when calling :
gr_message_sptr mesg = queue->delete_head_nowait();
from within a while loop (BTW the queue itself is being passed from a
Hello,
I did spent time working on GNU radio C++ API,
And I was stuck debugging in some point where I need to get the gr_foo to
retrieve the values of its members whereas I already instantiated
gr_foo_sptr instead.
Is there a way to fix this issue.
Example: I already instantiated gr_msg_queue_s
thank you Tom
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Hi,
I do have a bunch of files written in python and C/C++ describing a complete
transmission chain (Sources, Filters, Tx, Rx ...).
However I am intending to add new features from the FPGA API
(uhd::usrp::multi_usrp Class funtions like set_time_now()...) and those
features are to be written in a
> The FPGA interprets the timestamps and waits
> until the exact moment specified by the time to transmit.
> The timestamps specify an absolute time on the device
I would like to know what is the mechanism the FPGA is using to interpret
the timestamps. You are supposing there is two time referenc
Thank you josh,
I just want to be sure, are stream tags handled by timing of the FPGA (clock
ticks) or the timestamps are being inserted from within the host userspace,
because am getting too much variability on the latency when timestamps are
inserted in the OS.
regards.
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Hi,
I need to know if there is a way to retrieve a counter-like value from the
FPGA to timestamp the moment I sent a packet.
More precisely, I am sending a stream of packets from the host to radio, to
be sent to another radio in the Rx side.
Any clarifications are welcome,
Regards,
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Hi Ben,
Thanks for explanations,
I've been doing some theoretical calculations on the group delay estimation
and found that this part is giving negligible latency compared to the
Ethernet portion between USRP and host.
cheers.
2013/5/3 Naceur Amine El Ouni
> Thank you Marc,
>
> * Ok I wil
Thank you Marc,
* Ok I will try using a common clock ref and input PPS
* Scheduling the transmit and receive to within one tick of the 100 MHz
ADC clock: Can that be done into the host GNU radio code or am supposed to
move the code to the FPGA.
* Is that the samples count method to get accurate
thank you that was helpful
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Hi,
I would like to know if having set the configuration of one USRPN210 per
Ethernet interface is better (in terms of minimizing the latency towards the
Host) than the configuration of multiple USRPs connected to a host via a
unique Eth interface (eg. 192.168.10.x )
Which config. have better per
Hi,
I am sending a stream on packets between two USRP N210, and at the Tx side i
am setting a center freq. of 2.490 GHz for eg.
when outputting the Tune Result, I am always getting a difference of some
khz. (Target Freq: 2.49 GHz
thank you
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Hi all,
* Is it a correct to estimate by an ICMP echo-reply the latency between a
host and the USRP N210 at a giving instant.
* To estimate the delay in the Digital portion from the FPGA till the signal
is outputted by the antenna, is it a good way to fed the USRP by a signal
(similar as am going
Hi,
I am working on estimating the delay between a Tx and an Rx using a stream
of packets modulated in a BPSK scheme (1 Mb/s) with a pair of N210.
(Sampling of 8 Mbits/s)
I want to know if the latency added by the portion(*) of [ FPGA - DAC - RF
front end to the antenna *2 (Rx Part) ] could be de
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