Hi Lance,
On 12/14/06, seph 004 [EMAIL PROTECTED] wrote:
Hi
It seems the more I read through the fpga code, the more confused I get.
There are a few things I'm unsure about:
In the fpga DDC, are I and Q samples being generated from complex samples?
The adc_interface module just seems to
] wrote:
On Fri, Nov 10, 2006 at 07:23:07PM -0800, Oussama Sekkat wrote:
On 11/10/06, Eric Blossom [EMAIL PROTECTED] wrote:
Yes, I could enable the output pins from the host and just connect the
rx_a_a to one of the debug inputs in the master_control module. I
thaught it
wouldn't make
On 11/17/06, Eric Blossom [EMAIL PROTECTED] wrote:
On Fri, Nov 17, 2006 at 07:13:05PM -0800, Oussama Sekkat wrote:
Hi,
I am still trying to measure the digital output noise (from the LFRX_A
daughterboard).
In the verilog code I made sure to connect the rx_a_a input to the
debug1
input
On 11/17/06, Brian Padalino [EMAIL PROTECTED] wrote:
On 11/17/06, Oussama Sekkat [EMAIL PROTECTED] wrote:
Ok.
I fixed it now by making it a source instead. Thanks.
My output reading from the logic analyzer is now the following constant
16
bit value: 1100 0011
This seems to me
Ok :)
thanks Matt.
On 11/15/06, Matt Ettus [EMAIL PROTECTED] wrote:
Oussama Sekkat wrote:
Hi,
Quick question: I am using the daughterboards DEBUG IO pins , and I am
connecting them to my logic analyzer. I have to enter the threshold
value in my logic analyzer. I can choose between TTL
Hi,I'm trying to use my logic analyzer to measure the received noise.Here is how I proceed to do that. First in the verilog code, I connect the 12 bit rx_a_a ADC input to the io_rx_a DEBUG output by adding this line of code:
assign io_rx_a = {4'b, rx_a_a } I also make sure that the outputs of
On 11/10/06, Eric Blossom [EMAIL PROTECTED] wrote:
On Fri, Nov 10, 2006 at 06:01:02PM -0800, Oussama Sekkat wrote: Hi, I'm trying to use my logic analyzer to measure the received noise. Here is how I proceed to do that. First in the verilog code, I connect the
12 bit rx_a_aADC input
Hi Lance,On 11/7/06, seph 004 [EMAIL PROTECTED] wrote:
HiI've been bashing my head against this problem for a few weeks now, but I can't seem to figure it out. I've been making a few modifications to the verilog code, in particular the tx_buffer.v module. What I want to do is send a signal from
Hi Eric,On 11/4/06, Eric Blossom [EMAIL PROTECTED] wrote:
On Sat, Nov 04, 2006 at 05:10:14PM -0800, Oussama Sekkat wrote: Hi Dawei, If you want to start working on the FPGA code, you might want to start with the top level verilog modue located at gr-build/usrp/fpga/toplevel/usrp_std.v .
I don't
Hi,I am looking at the transmission buffer (tx_buffer.v) verilog code. So it seems that it uses two clock signals. the txclk signal is used to read from the fifo_4k while the usbclk signal is used to write to the fifo_4k.
What are the clock speeds for those clock signals? I believe I read in a
Hello,There is something that's unclear to me about recompiling the verilog code. The way I did it before was to create a project, add to it the top level module usrp_std.v and all the modules in the sdr_lib file. Then at every compile, the compiler complains and ask for such or such verilog
Hi Josh,
On 9/14/06, Josh Jennings [EMAIL PROTECTED] wrote:
Hi Oussama,
Yes the Linux version is not free. I am using the windows version. I am
working on Linux as well but I run windows on my laptop and I use the free
QuartusII software.
Figured.
I am studying the functionality of the
Hello,I am looking at the serial_io.v verilog module. It is my understanding that this module gets an address and data serially through the SDI input and sets some FPGA registers according to that input. Is the purpose of having such module to control some parameters directly from software such as
Hello,
I was looking at the AD9862 data sheet, and it seems that in the Transmith path, there is only one 14bit input but the chip outputs 2 Tx signals.
Does this mean that if we want to output two signals, the data has to be interleaved before being sent to the AD chip?
I am not sure why there
you once again for your help.Cheers,Oussama.On 8/21/06,
Eric Blossom [EMAIL PROTECTED] wrote:On Mon, Aug 21, 2006 at 12:32:11AM -0700, Oussama Sekkat wrote:
Thank you very much Eric. I tried it both ways and it works.Glad to hear it ;) For the second way, I enabled the debug outputs as you showed me
Hi,I generated a signal using the usrp_siggen.py function and tried to use the IO_pins on the basic TX board to monitor the digital output on a logic analyzer but it seems that no signal goes to those pins. Is there somehting I need to change in the verilog code to be able to use the debug IO
Hello,When the USRP is plugged in, the LED to the right of the USB controller blinks at a fast rate of about 3 times per second. Once a USRP application starts, that rate slows down to about 1 time per second. What controls the blinking of the LEDs? Is it the blink_leds.c function in the
Hi,I am looking at the tx_buffer module. From my understanding, that module does the interlacing of the data to be transmitted (2 I channels and 2 Q channels). Is that correct? Also, next to the bus_reset input declaration there is a comment saying Used here for the 257 hack to fix the FX2 bug.
HiI am looking at the usrp_std.v module and the schematics for the FPGA and the FX2/FPGA interface.It seems to me that the data of course arrives as a serial input to the FX2 chip. Then, it gets to the FPGA as a 16bit parallel input from the GPIF bus. That input is called usb_data in the FPGA.
Hi,quick question: In order to read the gpif.gpf file, do I need to download the GPIF Designer software from cypress.com?If I do, can that program run on Linux?Thanks,Oussama.
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Hi Matt,I am looking at the USRP FPGA/FX2 interface schematics. I see that there are different modules such as U412 and U101. Is there any documentation I could read about the role of those modules. I am basically trying to figure out how the data is sent from the Cypress FX2 to the usrp_std.v
I see. Thanks.Also, I was looking at the serial_io.v module but I am not sure what its purpose is or what it does.If I am not mistaken, it reads the data from the Cypress USB controller chip. What does it do to that data?
Oussama.On 7/12/06, Matt Ettus [EMAIL PROTECTED] wrote:
Oussama Sekkat wrote
be available on the FPGA.
Oussama.On 7/11/06, Eric Blossom [EMAIL PROTECTED] wrote:
On Mon, Jul 10, 2006 at 08:22:29PM -0700, Oussama Sekkat wrote: Hello everybody, I am still a beginner in the project so bare with me if my questions have obvious answers. I was looking at the verilog code for usrp_std.v
Hello everybody,I am still a beginner in the project so bare with me if my questions have obvious answers.I
was looking at the verilog code for usrp_std.v module. that module
containes the tx_chain.v module which uses a module called phase_acc. I
am not sure what this later module does? It takes
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