Hi Bowen,
I don't spend a lot of time on this ML but I'm very interested in this
project as I could make heavy use of it in the future. I currently work on
VHDL support in Verilator and I know that handling HDL
(Verilog/SystemVerilog/VHDL) is quite hard.
Using regex is a good idea although it's s
Hi All,
I have been playing around with the Codec2 vocoder block. I have a working
flowgraph where I put a C2 encoder and a C2 decoder back to back.
I'm puzzled with the expected stream format. In the coder, the intent seems
to create a vector of 50 bits (or bytes where the LSB contains the bit
v
