Andrew -
On Wed, Nov 08, 2006 at 01:15:50AM +1000, Andrew Rich wrote:
I bought a bitscope device which did 40MS/s and had a 32 kb buffer.
Was disappointed and sold it.
What I really need is a FPGA and fast A/D solution.
What I am trying to do is
1) Capture up to 200us of window data
2)
Friends -
On Sun, Oct 29, 2006 at 05:42:46PM -0800, Johnathan Corgan wrote:
On Sun, 2006-10-29 at 20:03 -0500, Kim Toms wrote:
I want to do a direction finding application in the 462 Mhz spectrum
(FRS, GMRS), and need a coherent set of receivers to process the
signals. Preferably from 3
Hi -
I'm bringing up a board
http://recycle.lbl.gov/llrf4/
with a hardware and software USB stack based on and (for this purpose)
equivalent to the GNU Radio design, and measured its USB data transfer
capabilities more carefully than I have done before. There is a
distant possibility someone
Uwe -
On Fri, Oct 27, 2006 at 08:35:22PM +0200, Uwe Bonnes wrote:
ldoolitt == ldoolitt [EMAIL PROTECTED] writes:
ldoolitt Hi - I'm bringing up a board http://recycle.lbl.gov/llrf4/
ldoolitt with a hardware and software USB stack based on and (for this
Some hints for your part list
Friends -
As a die-hard old-school unix programmer, I want to be able to grab data
from a USRP-like device, under control of a main loop based on
select(2). The comments in the source code of fusb are not encouraging.
Quoting from gnuradio-3.0/usrp/host/lib/fusb_linux.cc:
// Totally evil and
On Thu, Oct 12, 2006 at 12:10:23AM -0700, Oussama Sekkat wrote:
One of the input to the usrp_std module is SDI. From my understading, a
serial address and serial data is sent through that input in order to
control registers inside the FPGA. What I don't know is the origin of the
input. It
Eric -
On Fri, Sep 15, 2006 at 12:48:51PM -0700, Eric Blossom wrote:
I loved seeing the purist X86_64 systems -- the ones with no 32-bit code ;)
Why the he|| would I want to run 32-bit code on a 64-bit machine?
1/2 :-)
- Larry
___
ran both a Virtex4 and a Spartan3 board off of this.
http://recycle.lbl.gov/~ldoolitt/xguff.html
- Larry
___
Discuss-gnuradio mailing list
Discuss-gnuradio@gnu.org
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Friends -
On Fri, May 19, 2006 at 11:14:43PM -0400, David Bengtson wrote:
A significant amount of my work hours are
spent staring into
1) The Matlab IDE
2) Agilent's ADS
3) Microsoft Excel
and I'd really like the time to learn Verilog. While Computer algebra
packages are nice, if you
On Thu, Apr 06, 2006 at 06:55:57PM +0200, Martin Dvh wrote:
(Life would be so much easier if all the clocks on the usrp would first go
through the fpga.
Which could then upconvert/divide/pll/override/combine any clock in verilog
software.)
Rule 1 for digitizing RF: never let the clock
, that is derived from USRP.
Resetting n-1 buffers isn't good enough. :-p
You have to reset the FPGA buffer, the Cypress FX buffer,
and the host USB stack. My model code is at
http://recycle.lbl.gov/~ldoolitt/xguff.html
For a work-around, I suggest you drop the first 1M samples.
I did
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