On Thursday 16 October 2008 01:00:19 Jason Uher wrote:
> 2008/10/14 Daniel O'Connor <[EMAIL PROTECTED]>:
> > On Wednesday 15 October 2008 01:15:48 Sebastiaan Heunis wrote:
> >> always @(posedge clk)
> >> begin
> >> tap1 <= #1 input;
> >> tap2 <= #1 tap1;
> >> tap3 <= #1 tap2;
> >> end
> >>
> >>
2008/10/14 Daniel O'Connor <[EMAIL PROTECTED]>:
> On Wednesday 15 October 2008 01:15:48 Sebastiaan Heunis wrote:
>> always @(posedge clk)
>> begin
>> tap1 <= #1 input;
>> tap2 <= #1 tap1;
>> tap3 <= #1 tap2;
>> end
>>
>> the #1 ensures that tap1 gets updated before tap2?
>
> According to what I
On Wednesday 15 October 2008 01:15:48 Sebastiaan Heunis wrote:
> always @(posedge clk)
> begin
> tap1 <= #1 input;
> tap2 <= #1 tap1;
> tap3 <= #1 tap2;
> end
>
> the #1 ensures that tap1 gets updated before tap2?
According to what I have read with about synthesis tools the delays will be
igno
On Tue, Oct 14, 2008 at 10:45 AM, Sebastiaan Heunis <[EMAIL PROTECTED]> wrote:
> Hi
>
> Can someone with Verilog experience please help me with a question or
> two? I have done some VHDL before, so I am not entirely clueless.
>
> Is it possible to bit selects with an array of registers? How do I
Hi
Can someone with Verilog experience please help me with a question or
two? I have done some VHDL before, so I am not entirely clueless.
Is it possible to bit selects with an array of registers? How do I
select the upper eight bits from ram_array[2] if I have the following?
reg [15:0]
