On Tue, Sep 23, 2008 at 05:04:54PM +0200, Sebastiaan Heunis wrote:
> Hi
>
> I have a few questions to ask about the ADC if anyone could please
> help me? I know that it has a 12-bit output, so our output is between
> 0 and 4095. I would just like to know how this ADC input gets
> converted after
On Tue, Sep 23, 2008 at 10:08:02PM +0200, Sebastiaan Heunis wrote:
>
> I just don't know how the rx_dcoffset part works. I don't know where
> in the c++ or Python code the FR_ADC_OFFSET registers get written, so
> I can't follow it that well. Does this remove a DC offset introduced
> by the ADC
On Wed, Sep 24, 2008 at 5:51 PM, Sebastiaan Heunis <[EMAIL PROTECTED]> wrote:
> Brian
>
> Sorry to bother. I have one more question for now. I wrote a Python
> app to generate an input signal, convert it to 12-bit two's complement
> and then bitshift it left by 3 and sign-extend it to get it to t
Brian
Sorry to bother. I have one more question for now. I wrote a Python
app to generate an input signal, convert it to 12-bit two's complement
and then bitshift it left by 3 and sign-extend it to get it to the
representation used inside the FPGA. My question now is that if I
feed this input s
On Tue, Sep 23, 2008 at 4:54 PM, Sebastiaan Heunis <[EMAIL PROTECTED]> wrote:
> Brian
>
> Thanks. I understand the offset part then. Nothing happens if there
> is no DC offset. I want to simulate an FM signal coming from the
> TVRX, so the TVRX output is 20MHz, I understand that I then need to
>
Brian
Thanks. I understand the offset part then. Nothing happens if there
is no DC offset. I want to simulate an FM signal coming from the
TVRX, so the TVRX output is 20MHz, I understand that I then need to
write 2952790016 to the FR_RX_FREQ_0 register in the phase_acc. The
cordic will then mu
On Tue, Sep 23, 2008 at 4:08 PM, Sebastiaan Heunis <[EMAIL PROTECTED]> wrote:
> Brian
>
> Thanks for the reply. I see from this Verilog line that the adc input
> gets sign extended and gets 3 zeros at the back as you mentioned.
>
> rx_dcoffset #(`FR_ADC_OFFSET_0)
> rx_dcoffset0(.clock(clock),.enab
Brian
Thanks for the reply. I see from this Verilog line that the adc input
gets sign extended and gets 3 zeros at the back as you mentioned.
rx_dcoffset #(`FR_ADC_OFFSET_0)
rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_in({adc0[11],adc0,3'b0}),.adc_out(adc0_corr),
On Tue, Sep 23, 2008 at 11:04 AM, Sebastiaan Heunis <[EMAIL PROTECTED]> wrote:
> Hi
>
> I have a few questions to ask about the ADC if anyone could please
> help me? I know that it has a 12-bit output, so our output is between
> 0 and 4095. I would just like to know how this ADC input gets
> conv
Hi
I have a few questions to ask about the ADC if anyone could please
help me? I know that it has a 12-bit output, so our output is between
0 and 4095. I would just like to know how this ADC input gets
converted after leaving the adc_interface block in the FPGA. In other
words, how are positive
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