NaceurElOuni -
I think I'm having trouble understanding your question. I'm not sure what
you want to measure, or how you intend to measure it.
For starters, there isn't really a shared concept of 'time' between the
FPGA and the analog components. The FPGA operates in terms of clocks...
which
Hint 1: If both 210s are on the same PPS and frequency reference and the FPGA
clocks are synchronized to the PPS, you can schedule the transmit and receive
to within one tick of the 100 MHz ADC clock.
Hint 2: Cross correlate the transmitted and received samples. The lag will be
independent of
Thank you Marc,
* Ok I will try using a common clock ref and input PPS
* Scheduling the transmit and receive to within one tick of the 100 MHz
ADC clock: Can that be done into the host GNU radio code or am supposed to
move the code to the FPGA.
* Is that the samples count method to get
Hi Ben,
Thanks for explanations,
I've been doing some theoretical calculations on the group delay estimation
and found that this part is giving negligible latency compared to the
Ethernet portion between USRP and host.
cheers.
2013/5/3 Naceur Amine El Ouni naceuram...@gmail.com
Thank you
Hi,
I am working on estimating the delay between a Tx and an Rx using a stream
of packets modulated in a BPSK scheme (1 Mb/s) with a pair of N210.
(Sampling of 8 Mbits/s)
I want to know if the latency added by the portion(*) of [ FPGA - DAC - RF
front end to the antenna *2 (Rx Part) ] could be
