Hi Josh,
Thanks a lot for your help! We will try this after our E100 order arrives.
Josh Blum-3 wrote:
>
>
>> Thanks a lot for your help. Could you explain how to slow down the
>> FPGA/ADC
>> rate? How should we modify the firmware? Which part of the code should
>> we
>> look into? Thanks
> Thanks a lot for your help. Could you explain how to slow down the FPGA/ADC
> rate? How should we modify the firmware? Which part of the code should we
> look into? Thanks!
>
>
This is a host code modification.
see the clock_ctrl.cpp in host/lib/usrp/usrp_e100/
http://code.ettus.com/redmin
On 01/11/2011 10:18 PM, Alexander Chemeris wrote:
Hi Matt,
Thank you for your clarification.
What are the limits and steps/accuracy of ADC/DAC clock speed regulation?
E.g. is it possible to sample at 56MHz or 26 MHz and set sampling
clock with 1Hz precision?
You cannot get 1 Hz steps.
See ht
Hi Matt,
Thank you for your clarification.
What are the limits and steps/accuracy of ADC/DAC clock speed regulation?
E.g. is it possible to sample at 56MHz or 26 MHz and set sampling
clock with 1Hz precision?
On Wed, Jan 12, 2011 at 00:16, Matt Ettus wrote:
>
> As it is currently set up, there
Hey Matt,
Thanks a lot for your help. Could you explain how to slow down the FPGA/ADC
rate? How should we modify the firmware? Which part of the code should we
look into? Thanks!
Matt Ettus wrote:
>
>
> As it is currently set up, there are only 2 clock rates. The OMAP
> processor can ru
On 01/11/2011 03:35 PM, Miok Wah wrote:
Hi Philip,
Thanks a lot for your kind help!
From the description here:
http://elinux.org/OMAP_Power_Management#DVFS:_Dynamic_Voltage_and_Frequency_Scaling
I see that it's possible to change the operating frequency of the OMAP using
certain commands.
As far as I know, the decimation is after the ADC, so ADC rate doesn't change
after changing the clock rate. I'm happy to be corrected if it's not so. :)
That's correct. The ADC rates are fixed across all the products. That
vastly simplifies things both in the FPGA
DDC+CIC decimators, an
As it is currently set up, there are only 2 clock rates. The OMAP
processor can run at up to 720 MHz. This clock rate is independent of
the FPGA, ADC, and DAC clocks.
The ADC clock can run as high as 64 MS/s. The DAC always runs at
exactly double the rate of the ADC. The FPGA is normally
As far as I know, the decimation is after the ADC, so ADC rate doesn't change
after changing the clock rate. I'm happy to be corrected if it's not so. :)
Alexander Chemeris wrote:
>
> Hi,
>
> What about ADC/DAC clock rates?
>
>
> --
> Regards,
> Alexander Chemeris.
> http://www.fairwaves.
Hi Philip,
Thanks a lot for your kind help!
>From the description here:
http://elinux.org/OMAP_Power_Management#DVFS:_Dynamic_Voltage_and_Frequency_Scaling
I see that it's possible to change the operating frequency of the OMAP using
certain commands.
Do you know if E100 supports such commands
Hi,
On Mon, Jan 10, 2011 at 23:03, Philip Balister wrote:
> On 01/10/2011 09:25 AM, Miok Wah wrote:
>> We are planning to do some experiments with USRP E100. One advantage of
>> E100
>> that we are excited with is that
>> "The user can choose (at run time) a convenient clock rate".
>>
>> Our ques
On 01/10/2011 09:25 AM, Miok Wah wrote:
Hello list,
We are planning to do some experiments with USRP E100. One advantage of E100
that we are excited with is that
"The user can choose (at run time) a convenient clock rate".
Our question is:
1) When we change the clock rate changed, is the main
Hello list,
We are planning to do some experiments with USRP E100. One advantage of E100
that we are excited with is that
"The user can choose (at run time) a convenient clock rate".
Our question is:
1) When we change the clock rate changed, is the main clock rate changed, or
is it just change
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