"As I hinted at in an earlier email, what we've done is create a custom verilog load that takes the data lines after the FIFO but before the CIC filter and routes some of them out to IO pins on the daughtercard (which seem to be 0-3.3V LVTTL levels)."
Steven or anyone else. Is there any other or further work in this arena? I could find many uses for having access to IO pins on the daughter card. Actually all I need is one LVTTL pin for an output on my RFX1800. Is this already possible and I am just not seeing it? Thanks Jeff _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
