[Discuss-gnuradio] Bus widths and data rates

Hello, I have been trying to understand the tx and rx data paths through the AD9862 and the FPGA (standard configuration). RX side: - The two ADCs of the AD9862 push data onto two 12 bit buses - After the FPGA MUX the 16 bit I/Q signals pass into the assigned DDC - Are four extra bits

Re: [Discuss-gnuradio] Bus widths and data rates

On Jan 30, 2008 9:35 AM, TomasOMaille [EMAIL PROTECTED] wrote: Hello, I have been trying to understand the tx and rx data paths through the AD9862 and the FPGA (standard configuration). RX side: - The two ADCs of the AD9862 push data onto two 12 bit buses - After the FPGA MUX the 16

Re: [Discuss-gnuradio] Bus widths and data rates

Thanks Brian, That clears up a lot in my head. My Verilog knowledge is pretty primitive at this point. Tomas O'Maille ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio