Hi Marcus,
Thank you for your reply,
What I am aiming ultimately is to estimate the time delay a packet could
have when running through the following path:
HOST(1) =>[Ethernet]=> USRP(1)[FPGA-DAC-AnalogPath-Antenna] ==> On the air
==> The same path Reversed (USRP(2)) ==> HOST(1) or another HOS
Hi Naceur,
On 2013-10-02 21:57, Naceur wrote:
What I want to try with the USRP's FPGA is to send it a stream of
packets
(Header + Payload),
header field's length being known and fixed in advance, I need the
FPGA to
override a part of the Payload's field with its time register's
value and
Hello list,
=
I am a newbie in USRP FPGA programming,
I used once Xilinx ISE to execute some VHDL code, generated a bit file to
program a Virtex 4,
But now in the context of GNU Radio and USRP. I would like to know what are
the tools rec
