On Thu, Nov 16, 2006 at 01:11:15AM -0800, seph 004 wrote:
> Hi
>
> I'm still trying to figure out the problem in my code. I think that
> along the way I misunderstood the purpose of the write_count
> register. How does it actually work? WR triggers every time a 16 bit
> packet is ready from the F
Hi
I'm still trying to figure out the problem in my code. I think that along the
way I misunderstood the purpose of the write_count register. How does it
actually work? WR triggers every time a 16 bit packet is ready from the FX2
doesn't it?
The wreq trigger of the FIFO is triggered by (WR & ~
Hi Lance,On 11/7/06, seph 004 <[EMAIL PROTECTED]> wrote:
HiI've been bashing my head against this problem for a few weeks now, but I can't seem to figure it out. I've been making a few modifications to the verilog code, in particular the tx_buffer.v module. What I want to do is send a signal from t
HiI've been bashing my head against this problem for a few weeks now, but I can't seem to figure it out. I've been making a few modifications to the verilog code, in particular the tx_buffer.v module. What I want to do is send a signal from the pc and trap it in the fpga. I've tried doing this by r
