Hi,
We are using USRP-E100, but that requires us to find a Xilinx ISE first.
We will go on that but since we can get a USRP1,
we want to know how to update FPGA on USRP1 too.
We have already successfully compiled it in Quartus, and we want to have
a test first.
The file and the only file we have
On 08/25/2011 03:41 PM, xi yang wrote:
Hi, Philip,
Thanks!
If I got a USRP1, what files do I need to copy to /usr/share/uhd/images ?
And that's it? No additional operations?
Are you using a USRP1 or a USRP-E100?
Philip
Yooxi
2011/8/25 Philip Balister
On 08/25/2011 03:26 PM, xi yang wr
Hi, Philip,
Thanks!
If I got a USRP1, what files do I need to copy to /usr/share/uhd/images ?
And that's it? No additional operations?
Yooxi
2011/8/25 Philip Balister
> On 08/25/2011 03:26 PM, xi yang wrote:
>
>> Hi, Nick,
>>
>> Thanks a lot!
>> Do you know which file is same as usrp_std.v th
On 08/25/2011 03:26 PM, xi yang wrote:
Hi, Nick,
Thanks a lot!
Do you know which file is same as usrp_std.v that is responsible for binding
all modules together?
This one:
fpga/usrp2/top/E1x0/u1e_core.v
I think.
Philip
Yooxi
2011/8/25 Nick Foster
Yooxi,
The USRP1 used an Altera FPGA
Thanks, Josh!
Then we will find a Xilinx ISE and see what's the next step.
Yooxi
Josh Blum-3 wrote:
>
>
>
> On 08/24/2011 09:30 PM, xi yang wrote:
>> Hi, all,
>>
>> We have made a FPGA FFT module.
>> We downloaded the UHD source code from
>> https://github.com/EttusResearch/UHD-Mirror/arc
Hi, Nick,
Thanks a lot!
Do you know which file is same as usrp_std.v that is responsible for binding
all modules together?
Yooxi
2011/8/25 Nick Foster
> Yooxi,
>
> The USRP1 used an Altera FPGA. The USRP E100 uses a Xilinx Spartan-3A FPGA.
> The FPGA code you want to be modifying is in the fp
Yooxi,
The USRP1 used an Altera FPGA. The USRP E100 uses a Xilinx Spartan-3A FPGA.
The FPGA code you want to be modifying is in the fpga/usrp2/top/E1x0
directory.
--n
On Wed, Aug 24, 2011 at 9:30 PM, xi yang wrote:
> Hi, all,
>
> We have made a FPGA FFT module.
> We downloaded the UHD source c
On 08/24/2011 09:30 PM, xi yang wrote:
> Hi, all,
>
> We have made a FPGA FFT module.
> We downloaded the UHD source code from
> https://github.com/EttusResearch/UHD-Mirror/archives/master
> We modified the usrp_std.v under
> fpga/usrp1/toplevel/usrp_std/
> to link our FFT module between rx_buff
Hi, all,
We have made a FPGA FFT module.
We downloaded the UHD source code from
https://github.com/EttusResearch/UHD-Mirror/archives/master
We modified the usrp_std.v under
fpga/usrp1/toplevel/usrp_std/
to link our FFT module between rx_buffer and USB.
We have successfully compiled the usrp_std.qp
