Posting this to GR (as opposed to USRP) since it seems more theory.
Say I have an X300 and want to get DC - 200 MHz BW from a single daughter
card by combining two real sampled streams. The X300 ADCs (or within the
dual channel ADCs themselves) clocks can't be interleaved.
An argument is that on
Lou,
Many high-speed data converters actually interleave samples from multiple
lower speed ADCs. They delay clock, rather than the signal, which is much
easier. Even then, unless the delay is perfect, you get really bad spurs.
Mismatches in delay on the order of 100 fs can be a big problem.
So
In the spirit of voiding the warranty, physically invert the LVDS clock input
and output traces at the ADS62P48 with haywire and x-acto knife; the FPGA
may then not know the difference. Use it as sub-device A:AB at the full 200
Msps, then interleave the complex parts into a real stream once in GR.
