Brian-
> On 10/12/07, Jeff Brower <[EMAIL PROTECTED]> wrote:
> > I think the biggest concerns with Cyclone I are lack of multipliers and low
> > amount of
> > internal mem (26 kbyte for the EPC1C12).
>
> Understandable, but also remember that a CORDIC can perform a
> multiplication if you want i
On 10/12/07, Jeff Brower <[EMAIL PROTECTED]> wrote:
> I think the biggest concerns with Cyclone I are lack of multipliers and low
> amount of
> internal mem (26 kbyte for the EPC1C12).
Understandable, but also remember that a CORDIC can perform a
multiplication if you want it pipelined - and if y
Brian-
> > 2) Does your new FPGA code require the next-gen USRP, with Spartan 3 FPGA?
> > My understanding is that capacity is very
> > limited in the Cyclone, which is an old FPGA (around yr 2002 time-frame).
>
> If you have a single, specific application in mind, you should be able
> to reduc
Brian-
> > 2) Does your new FPGA code require the next-gen USRP, with Spartan 3 FPGA?
> > My understanding is that capacity is very
> > limited in the Cyclone, which is an old FPGA (around yr 2002 time-frame).
>
> If you have a single, specific application in mind, you should be able
> to reduc
On 10/12/07, Jeff Brower <[EMAIL PROTECTED]> wrote:
> ...
> 2) Does your new FPGA code require the next-gen USRP, with Spartan 3 FPGA?
> My understanding is that capacity is very
> limited in the Cyclone, which is an old FPGA (around yr 2002 time-frame).
If you have a single, specific applicatio
George-
Ok, I get it. Sounds very promising.
A couple of quick questions:
1) What about commands (meta-data) to help deal with latency? For example, 'if
you receive such-and-such request,
send this ACK'?
2) Does your new FPGA code require the next-gen USRP, with Spartan 3 FPGA? My
understa
