On 8/7/07, Reid N Kleckner <[EMAIL PROTECTED]> wrote:
> Hello,
>
> I've written a small Verilog module for the FPGA on the USRP to do phase
> recovery. I'd like to test it in isolation before I try it out on the board,
> but I'm having major problems feeding Quartus two 16 bit sine and cosine
> si
Reid N Kleckner wrote:
> Or do people just burn their Verilog code to the board to test it?
For pre-synthesis, RTL simulation and testing, I use Icarus Verilog
under Linux.
--
Johnathan Corgan
Corgan Enterprises LLC
http://corganenterprises.com
___
Hello,
I've written a small Verilog module for the FPGA on the USRP to do phase
recovery. I'd like to test it in isolation before I try it out on the board,
but I'm having major problems feeding Quartus two 16 bit sine and cosine
signals with a random phase offset. The idea is that q_out after t
