On Friday 28 July 2006 15:29, Eric Blossom wrote:
> > So if you wanted to use it you'd have to set up some local memory and
> > then copy data into that (from the FPGA) and then signal the host when a
> > "page" is done so it can program the PLX chip. Means you get an interrupt
> > every page which
On Fri, Jul 28, 2006 at 10:01:11AM +0930, Daniel O'Connor wrote:
> On Friday 28 July 2006 01:33, Eric Blossom wrote:
> > > A 9030 is target only, you'd need a 9054, 9056, 9060 or 9080 otherwise
> > > the performance would not be very great.
> >
> > Good point. I've written drivers using the 9080 b
On Friday 28 July 2006 01:39, Eric Blossom wrote:
> > method as well. No need to implement 802.3af (I think that's the
> > spec.). Even though there are no spare pairs to use for a DC feed on a
> > GigE CAT5 cable there are ethernet transformers which can isolate and
> > insert a common mode DC c
On Friday 28 July 2006 01:33, Eric Blossom wrote:
> > A 9030 is target only, you'd need a 9054, 9056, 9060 or 9080 otherwise
> > the performance would not be very great.
>
> Good point. I've written drivers using the 9080 before it was pretty
> easy to use. The scatter/gather stuff worked fine fo
The cost for the Xilinx PCI Express LogiCORE was $25,000, the last time
I looked. It may have dropped to $20,000. It can be used on a Virtex 2P
(for x1 and x4) or a Virtex 4 (for x1, x4, x8) operation.
The alternative is to use a PCIe PHY chip and then supply a PCIe Link
Layer / Transaction La
On Thu, Jul 27, 2006 at 04:39:43PM +1000, Jason Hecker wrote:
> >>(http://www.plxtech.com/products/io_accelerators/PCI9030/default.htm)
> >
> >That's one route, though 32-bit 33-MHz PCI is pretty much the bottom
> >of the barrel these days. Hence the interest in PCI-Express and/or
> >Express Card.
On Thu, Jul 27, 2006 at 04:02:00PM +0930, Daniel O'Connor wrote:
> On Thursday 27 July 2006 15:39, Jason Hecker wrote:
> > Would an extra bit of hardware such as a PCI card with PLX's PCI9030
> > breaking out to the USRP with something like an 80 wire IDE cable be
> > suitable for high bandwidth, l
On Thursday 27 July 2006 16:09, Jason Hecker wrote:
> > That's one route, though 32-bit 33-MHz PCI is pretty much the bottom
> > of the barrel these days. Hence the interest in PCI-Express and/or
> > Express Card.
>
> True. At a glance I couldn't see any alternative from PLX for faster
> PCI buss
The last time this came up, I think the problem was finding a gigabit chipset that didn't require a reflow oven and/or a 6-layer PCB... it's been a few months, it may be worth looking at again.R C
On 7/27/06, Stephane Fillod <[EMAIL PROTECTED]> wrote:
On Wed, 26 Jul 2006, Marcus Leech wrote:[...]>
On Wed, 26 Jul 2006, Marcus Leech wrote:
[...]
> o Is it time to think about moving away from USB for USRP? Perhaps to
>PCI-X 2.0, or PCI-Express?
http://comsec.com/wiki?USRPnotUSB
--
Stephane
PS: I would cast my vote for GigE.
___
Disc
(http://www.plxtech.com/products/io_accelerators/PCI9030/default.htm)
That's one route, though 32-bit 33-MHz PCI is pretty much the bottom
of the barrel these days. Hence the interest in PCI-Express and/or
Express Card.
True. At a glance I couldn't see any alternative from PLX for faster
PC
Was that really ethernet framing? Or just using the CAT5 cable as 4
differential pairs?
No, from memory he just used the driver chips and implemented his own
bit toggling and framing magic in the FPGA. He just used the drivers
and transformers to get the data on and off the cable.
If you di
On Thursday 27 July 2006 15:39, Jason Hecker wrote:
> Would an extra bit of hardware such as a PCI card with PLX's PCI9030
> breaking out to the USRP with something like an 80 wire IDE cable be
> suitable for high bandwidth, low latency and lowish cost?
>
> (http://www.plxtech.com/products/io_accel
On Thu, Jul 27, 2006 at 04:09:24PM +1000, Jason Hecker wrote:
> Would an extra bit of hardware such as a PCI card with PLX's PCI9030
> breaking out to the USRP with something like an 80 wire IDE cable be
> suitable for high bandwidth, low latency and lowish cost?
> (http://www.plxtech.com/produc
Would an extra bit of hardware such as a PCI card with PLX's PCI9030
breaking out to the USRP with something like an 80 wire IDE cable be
suitable for high bandwidth, low latency and lowish cost?
(http://www.plxtech.com/products/io_accelerators/PCI9030/default.htm)
You might be able to do giga
On Wed, Jul 26, 2006 at 10:11:14PM -0400, Nikhil wrote:
> On 7/26/06, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
> >
> >I'd vote for Gigabit Ethernet as an interface. It offers the following:
>
> Since you mention Gigabit Ethernet, I have to ask... are there any latency
> issues with it?
Laten
On 7/26/06, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
I'd vote for Gigabit Ethernet as an interface. It offers the following:
Since you mention Gigabit Ethernet, I have to ask... are there any latency issues with it?
Nikhil
___
Discuss-gnu
On Thursday 27 July 2006 02:23, Marcus Leech wrote:
> So, I read yesterday that Intel is going to start introducing quad-core
> CPUs sometime late this
> year, rather than 2007 as originally announced.
Let's hope they fix their bus architecture first otherwise they'll all be
starved for memory b
I'd vote for Gigabit Ethernet as an interface. It offers the following:
1. Place the USRP very close to the antenna.
2. Distribute the signal to multiple computers. (Multi-cast IP)
3. Very low cost infrastructure of Ethernet switches and cables.
4. Ethernet is easier to use across common platf
Eric Blossom wrote:
I see two paths that can get us there:
(1) dynamic partitioning of the flow graph across processors in
SMP/multi-core machines.
(2) m-blocks dynamically scheduled across processors on SMP/multi-core
Once N-cores gets sufficiently large (8 ?), I think we start movi
On Wed, Jul 26, 2006 at 12:53:06PM -0400, Marcus Leech wrote:
> So, I read yesterday that Intel is going to start introducing quad-core
> CPUs sometime late this
> year, rather than 2007 as originally announced.
>
> Two questions occur to me:
>
>o How can we best take advantage of the multip
So, I read yesterday that Intel is going to start introducing quad-core
CPUs sometime late this
year, rather than 2007 as originally announced.
Two questions occur to me:
o How can we best take advantage of the multiple CPU cores in Gnu Radio?
Being able to process larger bandwidths an
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