On 03/15/2010 10:24 PM, Per Zetterberg wrote:
4.) Do the PLL's on the daugherboard tune every time a C++ or Python
program
is run or every time the board is powered on? i.e. for phased arrays
will we
just need to calibrate every time the board is powered on or every
time we
take a given
Hi Matt, hope you had a good trip.
We've managed to work around the ambiguity using calibration, but we are
still interested in that other technique that you've mentioned earlier.
Also we have trouble understanding the meanings of the phase ambiguities we
are observing. We use a centre
4.) Do the PLL's on the daugherboard tune every time a C++ or Python
program
is run or every time the board is powered on? i.e. for phased arrays
will we
just need to calibrate every time the board is powered on or every
time we
take a given stream of data?
Every time you send the tune
I'll be away until the 22nd, but will give you an update on the possible
improved method when I get back.
Matt
On 03/11/2010 12:28 PM, ValentinG wrote:
It depends where you are measuring. The main 100 MHz clock should
always come up with the same phase.
Ok we've found the problem, we
It depends where you are measuring. The main 100 MHz clock should
always come up with the same phase.
Ok we've found the problem, we were measuring a 10MHz signal on the test
pins which is derived from 100MHz, therefore has a 10-way ambiguity, hence
different phases after power cycling...
Thanks a lot for the answers!
Yes all of our boards are USRP2s.
We do have a common PPS signal provided by the external signal generator. We
use code from the VRT branch and call set_time_at_next_pps for all 4 boards
to reset their times. Then we call start streaming for all 4 boards some
On 03/10/2010 06:39 AM, ValentinG wrote:
Thanks a lot for the answers!
Yes all of our boards are USRP2s.
We do have a common PPS signal provided by the external signal generator. We
use code from the VRT branch and call set_time_at_next_pps for all 4 boards
to reset their times. Then we call
Hi All,
We are trying to use 4 USRPs to extract the phase information due to
differences in positions of the antennas.
In a standard communications system an internally generated carrier is
locked IN PHASE with the incoming signal to perform downconversion (see
Figure 1.).
Hi All,
We are trying to use 4 USRPs to extract the phase information due to
differences in positions of the antennas.
In a standard communications system an internally generated carrier is
locked IN PHASE with the incoming signal to perform downconversion (see
Figure 1.).
On Tue, Mar 09, 2010 at 09:20:28AM -0800, ValentinG wrote:
Hi All,
We are trying to use 4 USRPs to extract the phase information due to
differences in positions of the antennas.
In a standard communications system an internally generated carrier is
locked IN PHASE with the incoming
On 03/09/2010 09:20 AM, ValentinG wrote:
Hi All,
We are trying to use 4 USRPs to extract the phase information due to
differences in positions of the antennas.
In a standard communications system an internally generated carrier is
locked IN PHASE with the incoming signal to perform
On Fri, May 12, 2006 at 01:27:14PM -0700, John Gilmore wrote:
What you're describing is currently tough with the basic tx since it's
effectively always on once you fire it up. If you underrun, the
FPGA will continue transmitting the same value to the DAC (which has
the upconverter in it),
Why would it take 8 clocks? Surely the hardware could do the hard
part (jam it to zero immediately) and the software could do the rest
(if it needs to taper off over 8 clocks, end with the right samples).
Ramping down results in a cleaner spectrum. Immediate shutoff splatters
the band.
On Sat, May 06, 2006 at 01:26:15PM -0700, Ges wrote:
Hi,
I am trying to do to and fro transmission using 2 USRP boards. I
have connected the tx and rx daughter cards together using SMA Tees
(3 SMA Tees connected together giving me 4 ports for connecting the
2 tx and 2 rx). I am trying
Hi,
I am trying to do to and fro transmission using 2 USRP boards. I have
connected the tx and rx daughter cards together using SMA Tees (3 SMA
Tees connected together giving me 4 ports for connecting the 2 tx and 2
rx). I am trying to do a TDMA type of transmisson. the TX on one usrp
transmits
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