On Monday 05 February 2007 20:20, Davide Anastasia wrote:
> I'm trying to realize a 1 bit quantizer on the FPGA, but I've some
> problem to understand how VHDL works!
>
> So, I hope you can help me.
> In the file /usrp/fpga/sdr_lib/rx_buffer.v there are two wire:
>
>wire [4:0] bitwidth;
>wi
Hi List,
I'm trying to realize a 1 bit quantizer on the FPGA, but I've some
problem to understand how VHDL works!
So, I hope you can help me.
In the file /usrp/fpga/sdr_lib/rx_buffer.v there are two wire:
wire [4:0] bitwidth;
wire [3:0] bitshift;
What's the function of these?
--
Davide An
