Eric-
> > > The LFRX has two separate antenna inputs, supplied to Vin-A and
> > > Vin-B. These are not I-Q data. USRP board FPGA logic would apply
> > > one mixer or two (30 MHz or less).
> >
> > [...]
> >
> > > The RFX2400 mixes with a 2.4 GHz osc and creates one set of I-Q 65
> > > MHz range s
On Thu, Jul 19, 2007 at 06:30:57AM -0700, Johnathan Corgan wrote:
> Jeff Brower wrote:
>
> > The LFRX has two separate antenna inputs, supplied to Vin-A and
> > Vin-B. These are not I-Q data. USRP board FPGA logic would apply
> > one mixer or two (30 MHz or less).
>
> [...]
>
> > The RFX2400 m
Johnathan-
> > The LFRX has two separate antenna inputs, supplied to Vin-A and
> > Vin-B. These are not I-Q data. USRP board FPGA logic would apply
> > one mixer or two (30 MHz or less).
>
> [...]
>
> > The RFX2400 mixes with a 2.4 GHz osc and creates one set of I-Q 65
> > MHz range signals, +
Jeff Brower wrote:
> The LFRX has two separate antenna inputs, supplied to Vin-A and
> Vin-B. These are not I-Q data. USRP board FPGA logic would apply
> one mixer or two (30 MHz or less).
[...]
> The RFX2400 mixes with a 2.4 GHz osc and creates one set of I-Q 65
> MHz range signals, +/-I on V
Roshan-
> > I think the OP is confused at what "signal processing" is happening on the
> > RF
> > daughterboard. Although some recent posts have said "none", there actually
> > is some
> > -- filters to separate the I and Q signals which were summed at the point
> > of original
> > transmissio
Ian-
> Ok, that makes sense. Looking back at this site
> (http://www.nd.edu/~jnl/sdr/docs/tutorials/4.html#tth_sEc2.1) I see
> that the DDC is combining the I and Q inputs to do complex
> multiplication. I originally thought it was multiplying the I and Q
> components separately, so that no inpu
Jeff Brower wrote:
I think the OP is confused at what "signal processing" is happening on the RF
daughterboard. Although some recent posts have said "none", there actually is
some
-- filters to separate the I and Q signals which were summed at the point of
original
transmission to make a singl
Ok, that makes sense. Looking back at this site
(http://www.nd.edu/~jnl/sdr/docs/tutorials/4.html#tth_sEc2.1) I see
that the DDC is combining the I and Q inputs to do complex
multiplication. I originally thought it was multiplying the I and Q
components separately, so that no input to Q would me
Johnathan-
> > I assume this also true for the BasicRX daughterboard? (Doesn't do
> > downconversion, but does do analog multiplication to get I and Q?)
>
> Almost. The boards don't do anything with the signal, but have separate
> I and Q inputs that go to the ADCs as is.
>
> On the FPGA, howev
Ian Larsen wrote:
> I assume this also true for the BasicRX daughterboard? (Doesn't do
> downconversion, but does do analog multiplication to get I and Q?)
Almost. The boards don't do anything with the signal, but have separate
I and Q inputs that go to the ADCs as is.
On the FPGA, however, the
The BasicRX daughterboard doesn't do anything signal processing, with
the exception of passing the signal through some transformers. It has
two separate I and Q inputs, which are passed down to the USRP, where
all the signal processing is actually done.
-Roshan
Ian Larsen wrote:
Thank you, t
Thank you, that's very helpful.
I assume this also true for the BasicRX daughterboard? (Doesn't do
downconversion, but does do analog multiplication to get I and Q?)
-Ian
On 7/18/07, Johnathan Corgan <[EMAIL PROTECTED]> wrote:
Ian Larsen wrote:
> I have a conceptual question about the USRP.
Hello,
I have a conceptual question about the USRP. Why are there 4 A/D
converters? Is it only for flexibility reasons, or can you acheive
double the sampling rate by clocking two of them 180 degrees of from
each other and interleaving the resulting data?
Also, it looks to me like the default
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